Thin effective oxide thickness (∼0.5 nm) and low leakage current gate dielectric for Ge MOS devices by plasma nitrided Al2O3 intermediate layer

Author(s):  
Yi-Gin Yang ◽  
Bing-Yue Tsui
2018 ◽  
Vol 65 (2) ◽  
pp. 680-686 ◽  
Author(s):  
Cheng-Jung Lee ◽  
Ke-Jing Lee ◽  
Yu-Chi Chang ◽  
Li-Wen Wang ◽  
Der-Wei Chou ◽  
...  

2014 ◽  
Vol 211 (4) ◽  
pp. 775-778 ◽  
Author(s):  
Xing Lu ◽  
Jun Ma ◽  
Zhaojun Liu ◽  
Huaxing Jiang ◽  
Tongde Huang ◽  
...  

2013 ◽  
Vol 34 (6) ◽  
pp. 738-740 ◽  
Author(s):  
Di Meng ◽  
Shuxun Lin ◽  
Cheng P. Wen ◽  
Maojun Wang ◽  
Jinyan Wang ◽  
...  

2011 ◽  
Author(s):  
T. Sato ◽  
J. Okayasu ◽  
T. Yamanouchi ◽  
T. Yashiro ◽  
J. Suzuki ◽  
...  

2012 ◽  
Vol 463-464 ◽  
pp. 1341-1345 ◽  
Author(s):  
Chong Liu ◽  
Xiao Li Fan

This essay aims to introduce development of gate dielectrics. In present-day society, Si-based MOS has met its physical limitation. Scientists are trying to find a better material to reduce the thickness and dimension of MOS devices. While substrate materials are required to have a higher mobility, gate dielectrics are expected to have high k, low Dit and low leakage current. I conclude dielectrics in both Si-based and Ge-based MOS devices and several measures to improve the properties of these gate dielectric materials. I also introduce studies on process in our group and some achievements we have got. Significantly, this essay points out the special interest in rare-earth oxides functioning as gate dielectrics in recent years and summarizes the advantages and problems should be resolved in future.


2008 ◽  
Vol 1091 ◽  
Author(s):  
Cheng-Chin Liu ◽  
Kuo-Jui Chang ◽  
Feng-Yu Yang ◽  
Ta-Chuan Liao ◽  
Huang-Chung Cheng

AbstractWe have successfully proposed a patterned P3HT thin-film transistor with cross-linked PVP as a passivation material which was cured at low temperature. The active P3HT layer was isolated via photolithographic technique and O2 plasma RIE etching process. In this method, the leakage current could be reduced effectively compared with that of non-patterned device. Although the mobility was degraded 40 %, but the on/off ratio was significantly improved by over three orders and also the subthreshold swing was compatible with the amorphous Si-TFTs (∼1.5 V/decade). Moreover, we also employed this low temperature curing PVP (120 0C) films as the gate dielectrics which exhibited excellent insulating property with high on/off ratio 1.58×104 and good subthreshold swing 1.66 V/decade.


2021 ◽  
Vol 12 (1) ◽  
Author(s):  
Mehrdad Rostami Osanloo ◽  
Maarten L. Van de Put ◽  
Ali Saadat ◽  
William G. Vandenberghe

AbstractTo realize effective van der Waals (vdW) transistors, vdW dielectrics are needed in addition to vdW channel materials. We study the dielectric properties of 32 exfoliable vdW materials using first principles methods. We calculate the static and optical dielectric constants and discover a large out-of-plane permittivity in GeClF, PbClF, LaOBr, and LaOCl, while the in-plane permittivity is high in BiOCl, PbClF, and TlF. To assess their potential as gate dielectrics, we calculate the band gap and electron affinity, and estimate the leakage current through the candidate dielectrics. We discover six monolayer dielectrics that promise to outperform bulk HfO2: HoOI, LaOBr, LaOCl, LaOI, SrI2, and YOBr with low leakage current and low equivalent oxide thickness. Of these, LaOBr and LaOCl are the most promising and our findings motivate the growth and exfoliation of rare-earth oxyhalides for their use as vdW dielectrics.


2009 ◽  
Vol 1194 ◽  
Author(s):  
Mathieu Moreau ◽  
Daniela Munteanu ◽  
Jean-Luc Autran ◽  
Florence Bellenger ◽  
Jérome Mitard ◽  
...  

AbstractWe present a one-dimensional simulation study of the capacitance-voltage (C-V) and current-voltage (I-V) characteristics in MOS devices with high mobility semiconductors (Ge and III-V materials) and non-conventional gate stack with high-κ dielectrics. The C-V quantum simulation code self-consistently solves the Schrödinger and Poisson equations and the electron transport through the gate stack is computed using the non-equilibrium Green’s function formalism (NEGF). Simulated C-V characteristics are successfully confronted to experimental data for various MOS structures with different semiconductors and dielectric stacks. Simulation of I-V characteristics reveals that gate leakage current strongly depends on gate stacks and substrate materials and predicts low leakage current for future CMOS devices with high mobility materials and high-κ dielectrics.


2021 ◽  
Vol 285 ◽  
pp. 129120
Author(s):  
Wenxin Liang ◽  
Hongfeng Zhao ◽  
Xiaoji Meng ◽  
Shaohua Fan ◽  
Qingyun Xie

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