Low Leakage Current Patterned Polymeric Transistors with PAG Assisted Cross-linking PVP as Gate Dielectric and Passivation Layers

2008 ◽  
Vol 1091 ◽  
Author(s):  
Cheng-Chin Liu ◽  
Kuo-Jui Chang ◽  
Feng-Yu Yang ◽  
Ta-Chuan Liao ◽  
Huang-Chung Cheng

AbstractWe have successfully proposed a patterned P3HT thin-film transistor with cross-linked PVP as a passivation material which was cured at low temperature. The active P3HT layer was isolated via photolithographic technique and O2 plasma RIE etching process. In this method, the leakage current could be reduced effectively compared with that of non-patterned device. Although the mobility was degraded 40 %, but the on/off ratio was significantly improved by over three orders and also the subthreshold swing was compatible with the amorphous Si-TFTs (∼1.5 V/decade). Moreover, we also employed this low temperature curing PVP (120 0C) films as the gate dielectrics which exhibited excellent insulating property with high on/off ratio 1.58×104 and good subthreshold swing 1.66 V/decade.

2018 ◽  
Vol 65 (2) ◽  
pp. 680-686 ◽  
Author(s):  
Cheng-Jung Lee ◽  
Ke-Jing Lee ◽  
Yu-Chi Chang ◽  
Li-Wen Wang ◽  
Der-Wei Chou ◽  
...  

2021 ◽  
pp. 106413
Author(s):  
Yuexin Yang ◽  
Zhuohui Xu ◽  
Tian Qiu ◽  
Honglong Ning ◽  
Jinyao Zhong ◽  
...  

2001 ◽  
Vol 685 ◽  
Author(s):  
Ching-Wei Lin ◽  
Li-Jing Cheng ◽  
Yin-Lung Lu ◽  
Huang-Chung Cheng

AbstractA simple process sequence for fabrication of low temperature polysilicon (LTPS) TFTs with self-aligned graded LDD structure was demonstrated. The graded LDD structure was self-aligned by side-etch of Al under the photo-resist followed by excimer laser irradiation for dopant activation and laterally diffusion. The graded LDD polysilicon TFTs were suitable for high-speed operation and active matrix switches applications because they possessed low-leakage-current characteristic without sacrificing driving capability significantly and increasing overlap capacitance. The leakage current of graded LDD polysilicon TFTs at Vd = 5V and Vg = −10V could attain to below 1pA/μm without any hygrogenation process, when proper LDD length and laser activation process were applied. The on/off current ratios of these devices were also above 108. Furthermore, due to graded dopant distribution in LDD regions, the drain electric field could be reduced further, and as a result, graded LDD polysilicon TFTs provided high reliability for high voltage operation.


RSC Advances ◽  
2014 ◽  
Vol 4 (36) ◽  
pp. 18493-18502 ◽  
Author(s):  
Jagan Singh Meena ◽  
Min-Ching Chu ◽  
Ranjodh Singh ◽  
Chung-Shu Wu ◽  
Umesh Chand ◽  
...  

Low-temperature process PS-b-PMMA composite film as gate dielectric deposited over plastic substrate, which exhibits high surface energy, high air stability, very low leakage current and better dielectric constant compared to their conventional polymer dielectrics for use in ZnO–TFT applications.


2014 ◽  
Vol 211 (4) ◽  
pp. 775-778 ◽  
Author(s):  
Xing Lu ◽  
Jun Ma ◽  
Zhaojun Liu ◽  
Huaxing Jiang ◽  
Tongde Huang ◽  
...  

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