Image processing system architecture using parallel arrays of digital signal processors

1993 ◽  
Author(s):  
Shirish P. Kshirsagar ◽  
Clifford A. Hobson ◽  
David A. Hartley ◽  
David M. Harvey
Keyword(s):  
Image Processing ◽  
System Architecture ◽  
Processing System ◽  
Digital Signal ◽  
Digital Signal Processors ◽  
Image Processing System ◽  
Parallel Arrays ◽  
Signal Processors

Research on Software Optimization of Real-Time Processing System Based on DSP

2011 ◽  
Vol 130-134 ◽  
pp. 2944-2947
Author(s):  
Ming Ju Gong ◽  
Yuan Lai Liu
Keyword(s):  
Real Time ◽  
Processing System ◽  
Digital Signal ◽  
Electron System ◽  
Digital Signal Processors ◽  
Time Requirement ◽  
Real Time Processing ◽  
The Real ◽  
Software Optimization ◽  
Signal Processors

The Digital Signal Processors of TI C6000 series, have a structure called VLIW and a Harvard structure, and a electron system based on DSPs can meet the real-time requirement depending on making full use of the structures by its software. Therefore the executing efficiency of software will directly affect the real-time character of the whole system. In this article, several methods of software optimization for C6000 DSPs are summarized, including the use of intrinsics, data accessing band-width and software pipelining etc. Using these methods to optimize the C code software can mostly solve the bad real-time problems in processing and then the system can meet the real-time requirement.

Software pattern recognition applied to nanodiffraction patterns from a STEM instrument

1986 ◽  
Vol 44 ◽  
pp. 694-695
Author(s):  
G.Y. Fan ◽  
J.M. Cowley
Keyword(s):  
Image Processing ◽  
Pattern Recognition ◽  
Computer Software ◽  
Processing System ◽  
Light Level ◽  
Host Computer ◽  
Low Light ◽  
Image Processing System ◽  
Recent Developments ◽  
On Line

In recent developments, the ASU HB5 has been modified so that the timing, positioning, and scanning of the finely focused electron probe can be entirely controlled by a host computer. This made the asynchronized handshake possible between the HB5 STEM and the image processing system which consists of host computer (PDP 11/34), DeAnza image processor (IP 5000) which is interfaced with a low-light level TV camera, array processor (AP 400) and various peripheral devices. This greatly facilitates the pattern recognition technique initiated by Monosmith and Cowley. Software called NANHB5 is under development which, instead of employing a set of photo-diodes to detect strong spots on a TV screen, uses various software techniques including on-line fast Fourier transform (FFT) to recognize patterns of greater complexity, taking advantage of the sophistication of our image processing system and the flexibility of computer software.

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