scholarly journals Massively parallel ultrafast random bit generation with a chip-scale laser

Science ◽  
2021 ◽  
Vol 371 (6532) ◽  
pp. 948-952 ◽  
Author(s):  
Kyungduk Kim ◽  
Stefan Bittner ◽  
Yongquan Zeng ◽  
Stefano Guazzotti ◽  
Ortwin Hess ◽  
...  
Keyword(s):  
Energy Efficient ◽  
Secure Communication ◽  
High Performance ◽  
Random Number ◽  
Random Number Generation ◽  
Massively Parallel ◽  
Stochastic Noise ◽  
Potential Applications ◽  
Lasing Modes ◽  
High Performance Computation

Random numbers are widely used for information security, cryptography, stochastic modeling, and quantum simulations. Key technical challenges for physical random number generation are speed and scalability. We demonstrate a method for ultrafast generation of hundreds of random bit streams in parallel with a single laser diode. Spatiotemporal interference of many lasing modes in a specially designed cavity is introduced as a scheme for greatly accelerated random bit generation. Spontaneous emission, caused by quantum fluctuations, produces stochastic noise that makes the bit streams unpredictable. We achieve a total bit rate of 250 terabits per second with off-line postprocessing, which is more than two orders of magnitude higher than the current postprocessing record. Our approach is robust, compact, and energy-efficient, with potential applications in secure communication and high-performance computation.

scholarly journals Cryptographically Secure Pseudo-Random Number Generator IP-Core Based on SHA2 Algorithm

Sensors ◽  
2020 ◽  
Vol 20 (7) ◽  
pp. 1869 ◽  
Author(s):  
Luca Baldanzi ◽  
Luca Crocetti ◽  
Francesco Falaschi ◽  
Matteo Bertolucci ◽  
Jacopo Belli ◽  
...  
Keyword(s):  
High Performance ◽  
Random Number ◽  
Random Number Generator ◽  
Random Number Generation ◽  
Random Numbers ◽  
Generation Process ◽  
Number Generator ◽  
Ip Core ◽  
Pseudo Random Number ◽  
Pseudo Random Number Generator

In the context of growing the adoption of advanced sensors and systems for active vehicle safety and driver assistance, an increasingly important issue is the security of the information exchanged between the different sub-systems of the vehicle. Random number generation is crucial in modern encryption and security applications as it is a critical task from the point of view of the robustness of the security chain. Random numbers are in fact used to generate the encryption keys to be used for ciphers. Consequently, any weakness in the key generation process can potentially leak information that can be used to breach even the strongest cipher. This paper presents the architecture of a high performance Random Number Generator (RNG) IP-core, in particular a Cryptographically Secure Pseudo-Random Number Generator (CSPRNG) IP-core, a digital hardware accelerator for random numbers generation which can be employed for cryptographically secure applications. The specifications used to develop the proposed project were derived from dedicated literature and standards. Subsequently, specific architecture optimizations were studied to achieve better timing performance and very high throughput values. The IP-core has been validated thanks to the official NIST Statistical Test Suite, in order to evaluate the degree of randomness of the numbers generated in output. Finally the CSPRNG IP-core has been characterized on relevant Field Programmable Gate Array (FPGA) and ASIC standard-cell technologies.

A Low-Cost Highly Reliable Spintronic True Random Number Generator Circuit for Secure Cryptography

SPIN ◽  
2019 ◽  
Vol 10 (01) ◽  
pp. 2050003 ◽  
Author(s):  
Iman Alibeigi ◽  
Abdolah Amirany ◽  
Ramin Rajaei ◽  
Mahmoud Tabandeh ◽  
Saeed Bagheri Shouraki
Keyword(s):  
High Speed ◽  
High Performance ◽  
Random Number ◽  
Low Cost ◽  
Random Number Generator ◽  
Magnetic Tunnel Junction ◽  
Random Number Generation ◽  
Cmos Technology ◽  
Random Numbers ◽  
Number Generation

Generation of random numbers is one of the most important steps in cryptographic algorithms. High endurance, high performance and low energy consumption are the attractive features offered by the Magnetic Tunnel Junction (MTJ) devices. Therefore, they have been considered as one of the promising candidates for next-generation digital integrated circuits. In this paper, a new circuit design for true random number generation using MTJs is proposed. Our proposed circuit offers a high speed, low power and a truly random number generation. In our design, we employed two MTJs that are configured in special states. Generated random bit at the output of the proposed circuit is returned to the write circuit to be written in the relevant cell for the next random generation. In a random bitstream, all bits must have the same chance of being “0”or “1”. We have proposed a new XOR-based method in this paper to resolve this issue in multiple random generators that produce truly random numbers with a different number of ones and zeros in the output stream. The simulation results using a 45[Formula: see text]nm CMOS technology with a special model of MTJ validated the advantages offered by the proposed circuit.

scholarly journals Speed improvement of the quantum factorization algorithm of P. Shor by upgrade its classical part

2020 ◽  
Vol 224 ◽  
pp. 01016
Author(s):  
Larissa Cherckesova ◽  
Olga Safaryan ◽  
Pavel Razumov ◽  
Irina Pilipenko ◽  
Yuriy Ivanov ◽  
...  
Keyword(s):  
High Performance ◽  
Random Number ◽  
Quantum Algorithm ◽  
Random Number Generation ◽  
Practical Application ◽  
Standard Quantum ◽  
Factorization Algorithm ◽  
Shor's Algorithm ◽  
Classical Part ◽  
Shor’S Quantum Algorithm

This report discusses Shor’s quantum factorization algorithm and ρ–Pollard’s factorization algorithm. Shor’s quantum factorization algorithm consists of classical and quantum parts. In the classical part, it is proposed to use Euclidean algorithm, to find the greatest common divisor (GCD), but now exist large number of modern algorithms for finding GCD. Results of calculations of 8 algorithms were considered, among which algorithm with lowest execution rate of task was identified, which allowed the quantum algorithm as whole to work faster, which in turn provides greater potential for practical application of Shor’s quantum algorithm. Standard quantum Shor’s algorithm was upgraded by replacing the binary algorithm with iterative shift algorithm, canceling random number generation operation, using additive chain algorithm for raising to power. Both Shor’s algorithms (standard and upgraded) are distinguished by their high performance, which proves much faster and insignificant increase in time in implementation of data processing. In addition, it was possible to modernize Shor’s quantum algorithm in such way that its efficiency turned out to be higher than standard algorithm because classical part received an improvement, which allows an increase in speed by 12%.

scholarly journals Fast Number Theoretic Transform for Ring-LWE on 8-bit AVR Embedded Processor

Sensors ◽  
2020 ◽  
Vol 20 (7) ◽  
pp. 2039 ◽  
Author(s):  
Hwajeong Seo ◽  
Hyeokdong Kwon ◽  
Yongbeen Kwon ◽  
Kyungho Kim ◽  
Seungju Choi ◽  
...  
Keyword(s):  
Random Sampling ◽  
High Performance ◽  
Random Number ◽  
Assembly Language ◽  
Random Number Generator ◽  
Random Number Generation ◽  
Optimization Techniques ◽  
Security Level ◽  
Reduction Techniques ◽  
Novel Approach

In this paper, we optimized Number Theoretic Transform (NTT) and random sampling operations on low-end 8-bit AVR microcontrollers. We focused on the optimized modular multiplication with secure countermeasure (i.e., constant timing), which ensures high performance and prevents timing attack and simple power analysis. In particular, we presented combined Look-Up Table (LUT)-based fast reduction techniques in a regular fashion. This novel approach only requires two times of LUT access to perform the whole modular reduction routine. The implementation is carefully written in assembly language, which reduces the number of memory access and function call routines. With LUT-based optimization techniques, proposed NTT implementations outperform the previous best results by 9.0% and 14.6% for 128-bit security level and 256-bit security level, respectively. Furthermore, we adopted the most optimized AES software implementation to improve the performance of pseudo random number generation for random sampling operation. The encryption of AES-256 counter (CTR) mode used for random number generator requires only 3184 clock cycles for 128-bit data input, which is 9.5% faster than previous state-of-art results. Finally, proposed methods are applied to the whole process of Ring-LWE key scheduling and encryption operations, which require only 524,211 and 659,603 clock cycles for 128-bit security level, respectively. For the key generation of 256-bit security level, 1,325,171 and 1,775,475 clock cycles are required for H/W and S/W AES-based implementations, respectively. For the encryption of 256-bit security level, 1,430,601 and 2,042,474 clock cycles are required for H/W and S/W AES-based implementations, respectively.

Random Number Generation with Entropy Sources in the Graphics Processing Units

2012 ◽  
Vol 268-270 ◽  
pp. 1863-1868
Author(s):  
Yong Jin Yeom
Keyword(s):  
Graphics Processing Units ◽  
Secure Communication ◽  
Random Number ◽  
Random Number Generator ◽  
Binary Sequence ◽  
Random Number Generation ◽  
Random Number Generators ◽  
Computing Environments ◽  
Graphics Processing ◽  
Modern Cryptography

The random number generator (RNG) is indispensable to modern cryptography since cryptographic services make use of random numbers for deriving encryption keys or nonces in protocols for secure communication. Operating systems like Linux and Windows provide built-in random number generators which can be accessed by cryptographic modules and other processes. If the system fails to collect sufficient entropy from the operating environment, the output from the RNG is blocked or becomes less secure. In this paper, we propose a method providing sufficient entropy to RNGs using graphics processing units. By estimating run-time of the kernel function in GPU, we can gather noisy data with bias. After the distillation process, we obtain a binary sequence for entropy input to the deterministic part of RNG. Our scheme was implemented on the computing environments using NVIDIA’s GPU GTX 580 and GTX 610M.

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