Fast Number Theoretic Transform for Ring-LWE on 8-bit AVR Embedded Processor

In this paper, we optimized Number Theoretic Transform (NTT) and random sampling operations on low-end 8-bit AVR microcontrollers. We focused on the optimized modular multiplication with secure countermeasure (i.e., constant timing), which ensures high performance and prevents timing attack and simple power analysis. In particular, we presented combined Look-Up Table (LUT)-based fast reduction techniques in a regular fashion. This novel approach only requires two times of LUT access to perform the whole modular reduction routine. The implementation is carefully written in assembly language, which reduces the number of memory access and function call routines. With LUT-based optimization techniques, proposed NTT implementations outperform the previous best results by 9.0% and 14.6% for 128-bit security level and 256-bit security level, respectively. Furthermore, we adopted the most optimized AES software implementation to improve the performance of pseudo random number generation for random sampling operation. The encryption of AES-256 counter (CTR) mode used for random number generator requires only 3184 clock cycles for 128-bit data input, which is 9.5% faster than previous state-of-art results. Finally, proposed methods are applied to the whole process of Ring-LWE key scheduling and encryption operations, which require only 524,211 and 659,603 clock cycles for 128-bit security level, respectively. For the key generation of 256-bit security level, 1,325,171 and 1,775,475 clock cycles are required for H/W and S/W AES-based implementations, respectively. For the encryption of 256-bit security level, 1,430,601 and 2,042,474 clock cycles are required for H/W and S/W AES-based implementations, respectively.

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Cryptographically Secure Pseudo-Random Number Generator IP-Core Based on SHA2 Algorithm

Sensors ◽

10.3390/s20071869 ◽

2020 ◽

Vol 20 (7) ◽

pp. 1869 ◽

Cited By ~ 2

Author(s):

Luca Baldanzi ◽

Luca Crocetti ◽

Francesco Falaschi ◽

Matteo Bertolucci ◽

Jacopo Belli ◽

...

Keyword(s):

High Performance ◽

Random Number ◽

Random Number Generator ◽

Random Number Generation ◽

Random Numbers ◽

Generation Process ◽

Number Generator ◽

Ip Core ◽

Pseudo Random Number ◽

Pseudo Random Number Generator

In the context of growing the adoption of advanced sensors and systems for active vehicle safety and driver assistance, an increasingly important issue is the security of the information exchanged between the different sub-systems of the vehicle. Random number generation is crucial in modern encryption and security applications as it is a critical task from the point of view of the robustness of the security chain. Random numbers are in fact used to generate the encryption keys to be used for ciphers. Consequently, any weakness in the key generation process can potentially leak information that can be used to breach even the strongest cipher. This paper presents the architecture of a high performance Random Number Generator (RNG) IP-core, in particular a Cryptographically Secure Pseudo-Random Number Generator (CSPRNG) IP-core, a digital hardware accelerator for random numbers generation which can be employed for cryptographically secure applications. The specifications used to develop the proposed project were derived from dedicated literature and standards. Subsequently, specific architecture optimizations were studied to achieve better timing performance and very high throughput values. The IP-core has been validated thanks to the official NIST Statistical Test Suite, in order to evaluate the degree of randomness of the numbers generated in output. Finally the CSPRNG IP-core has been characterized on relevant Field Programmable Gate Array (FPGA) and ASIC standard-cell technologies.

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A Low-Cost Highly Reliable Spintronic True Random Number Generator Circuit for Secure Cryptography

SPIN ◽

10.1142/s2010324720500034 ◽

2019 ◽

Vol 10 (01) ◽

pp. 2050003 ◽

Cited By ~ 1

Author(s):

Iman Alibeigi ◽

Abdolah Amirany ◽

Ramin Rajaei ◽

Mahmoud Tabandeh ◽

Saeed Bagheri Shouraki

Keyword(s):

High Speed ◽

High Performance ◽

Random Number ◽

Low Cost ◽

Random Number Generator ◽

Magnetic Tunnel Junction ◽

Random Number Generation ◽

Cmos Technology ◽

Random Numbers ◽

Number Generation

Generation of random numbers is one of the most important steps in cryptographic algorithms. High endurance, high performance and low energy consumption are the attractive features offered by the Magnetic Tunnel Junction (MTJ) devices. Therefore, they have been considered as one of the promising candidates for next-generation digital integrated circuits. In this paper, a new circuit design for true random number generation using MTJs is proposed. Our proposed circuit offers a high speed, low power and a truly random number generation. In our design, we employed two MTJs that are configured in special states. Generated random bit at the output of the proposed circuit is returned to the write circuit to be written in the relevant cell for the next random generation. In a random bitstream, all bits must have the same chance of being “0”or “1”. We have proposed a new XOR-based method in this paper to resolve this issue in multiple random generators that produce truly random numbers with a different number of ones and zeros in the output stream. The simulation results using a 45[Formula: see text]nm CMOS technology with a special model of MTJ validated the advantages offered by the proposed circuit.

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True Random Number Generator Based on Fibonacci-Galois Ring Oscillators for FPGA

Applied Sciences ◽

10.3390/app11083330 ◽

2021 ◽

Vol 11 (8) ◽

pp. 3330

Author(s):

Pietro Nannipieri ◽

Stefano Di Matteo ◽

Luca Baldanzi ◽

Luca Crocetti ◽

Jacopo Belli ◽

...

Keyword(s):

Field Programmable Gate Array ◽

Random Number ◽

Random Number Generator ◽

Random Number Generation ◽

Galois Ring ◽

Number Generator ◽

True Random Number Generator ◽

Number Generation ◽

Field Programmable ◽

Gate Array

Random numbers are widely employed in cryptography and security applications. If the generation process is weak, the whole chain of security can be compromised: these weaknesses could be exploited by an attacker to retrieve the information, breaking even the most robust implementation of a cipher. Due to their intrinsic close relationship with analogue parameters of the circuit, True Random Number Generators are usually tailored on specific silicon technology and are not easily scalable on programmable hardware, without affecting their entropy. On the other hand, programmable hardware and programmable System on Chip are gaining large adoption rate, also in security critical application, where high quality random number generation is mandatory. The work presented herein describes the design and the validation of a digital True Random Number Generator for cryptographically secure applications on Field Programmable Gate Array. After a preliminary study of literature and standards specifying requirements for random number generation, the design flow is illustrated, from specifications definition to the synthesis phase. Several solutions have been studied to assess their performances on a Field Programmable Gate Array device, with the aim to select the highest performance architecture. The proposed designs have been tested and validated, employing official test suites released by NIST standardization body, assessing the independence from the place and route and the randomness degree of the generated output. An architecture derived from the Fibonacci-Galois Ring Oscillator has been selected and synthesized on Intel Stratix IV, supporting throughput up to 400 Mbps. The achieved entropy in the best configuration is greater than 0.995.

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Self-clocking fast and variation tolerant true random number generator based on a stochastic mott memristor

10.21203/rs.3.rs-118145/v1 ◽

2020 ◽

Author(s):

Gwangmin Kim ◽

Jae Hyun In ◽

Hakseung Rhee ◽

Woojoon Park ◽

Hanchan Song ◽

...

Keyword(s):

Random Number ◽

Random Number Generator ◽

Random Number Generation ◽

Harsh Environments ◽

Random Numbers ◽

Number Generator ◽

High Tolerance ◽

Stochastic Oscillation ◽

Advanced Method ◽

Intrinsic Stochasticity

Abstract The intrinsic stochasticity of the memristor can be used to generate true random numbers, essential for non-decryptable hardware-based security devices. Here we propose a novel and advanced method to generate true random numbers utilizing the stochastic oscillation behavior of a NbOx mott memristor, exhibiting self-clocking, fast and variation tolerant characteristics. The random number generation rate of the device can be at least 40 kbs-1, which is the fastest record compared with previous volatile memristor-based TRNG devices. Also, its dimensionless operating principle provides high tolerance against both ambient temperature variation and device-to-device variation, enabling robust security hardware applicable in harsh environments.

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Pseudo-random number generation using a 3-state cellular automaton

International Journal of Modern Physics C ◽

10.1142/s0129183117500784 ◽

2017 ◽

Vol 28 (06) ◽

pp. 1750078 ◽

Cited By ~ 5

Author(s):

Kamalika Bhattacharjee ◽

Dipanjyoti Paul ◽

Sukanta Das

Keyword(s):

Cellular Automaton ◽

Random Number ◽

Random Number Generator ◽

Random Number Generation ◽

Number Generator ◽

Number Generation ◽

Pseudo Random Number ◽

Empirical Tests ◽

Pseudo Random Number Generator

This paper investigates the potentiality of pseudo-random number generation of a 3-neighborhood 3-state cellular automaton (CA) under periodic boundary condition. Theoretical and empirical tests are performed on the numbers, generated by the CA, to observe the quality of it as pseudo-random number generator (PRNG). We analyze the strength and weakness of the proposed PRNG and conclude that the selected CA is a good random number generator.

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SRAM Based Random Number Generator for Non-Repeating Pattern Generation

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.573.181 ◽

2014 ◽

Vol 573 ◽

pp. 181-186 ◽

Cited By ~ 3

Author(s):

G.P. Ramesh ◽

A. Rajan

Keyword(s):

Random Number ◽

Statistical Tests ◽

Random Number Generator ◽

Random Number Generation ◽

Pattern Generation ◽

Storage Device ◽

Number Generator ◽

Random Number Generators ◽

Field Programmable ◽

The Look

—Field-programmable gate array (FPGA) optimized random number generators (RNGs) are more resource-efficient than software-optimized RNGs because they can take advantage of bitwise operations and FPGA-specific features. A random number generator (RNG) is a computational or physical device designed to generate a sequence of numbers or symbols that lack any pattern, i.e. appear random. The many applications of randomness have led to the development of several different methods for generating random data. Several computational methods for random number generation exist, but often fall short of the goal of true randomness though they may meet, with varying success, some of the statistical tests for randomness intended to measure how unpredictable their results are (that is, to what degree their patterns are discernible).LUT-SR Family of Uniform Random Number Generators are able to handle randomness only based on seeds that is loaded in the look up table. To make random generation efficient, we propose new approach based on SRAM storage device.Keywords: RNG, LFSR, SRAM

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LFSR-Keyed MUX for Random Number Generation in Nano Communication Using QCA

Quantum Cryptography and the Future of Cyber Security - Advances in Information Security, Privacy, and Ethics ◽

10.4018/978-1-7998-2253-0.ch004 ◽

2020 ◽

pp. 70-83

Author(s):

Padmapriya Praveenkumar ◽

Santhiya Devi R. ◽

Amirtharajan Rengarajan ◽

John Bosco Balaguru Rayappan

Keyword(s):

Cellular Automata ◽

Random Number ◽

Random Number Generator ◽

Random Number Generation ◽

Linear Feedback ◽

Innovative Technology ◽

Minimal Size ◽

Quantum Cellular Automata ◽

Technology Roadmap ◽

Feedback Shift Register

Nano industries have been successful trendsetters for the past 30 years, in escalating the speed and dropping the power necessities of nanoelectronic devices. According to Moore's law and the assessment created by the international technology roadmap for semiconductors, beyond 2020, there will be considerable restrictions in manufacturing IC's based on CMOS technologies. As a result, the next prototype to get over these effects is quantum-dot cellular automata (QCA). In this chapter, an efficient quantum cellular automata (QCA) based random number generator (RNG) is proposed. QCA is an innovative technology in the nano regime which guarantees large device density, less power dissipation, and minimal size as compared to the various CMOS technologies. With the aim to maximise the randomness in the proposed nano communication, a linear feedback shift register (LFSR) keyed multiplexer with ring oscillators is developed. The developed RNG is simulated using a quantum cellular automata (QCA) simulator tool.

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Pseudo Random Number Generation through Reinforcement Learning and Recurrent Neural Networks

Algorithms ◽

10.3390/a13110307 ◽

2020 ◽

Vol 13 (11) ◽

pp. 307

Author(s):

Luca Pasqualini ◽

Maurizio Parton

Keyword(s):

Reinforcement Learning ◽

Random Number ◽

Short Term Memory ◽

Random Number Generator ◽

Random Number Generation ◽

Time Step ◽

Software Applications ◽

Pseudo Random Number ◽

Markov Decision ◽

Partially Observable

A Pseudo-Random Number Generator (PRNG) is any algorithm generating a sequence of numbers approximating properties of random numbers. These numbers are widely employed in mid-level cryptography and in software applications. Test suites are used to evaluate the quality of PRNGs by checking statistical properties of the generated sequences. These sequences are commonly represented bit by bit. This paper proposes a Reinforcement Learning (RL) approach to the task of generating PRNGs from scratch by learning a policy to solve a partially observable Markov Decision Process (MDP), where the full state is the period of the generated sequence, and the observation at each time-step is the last sequence of bits appended to such states. We use Long-Short Term Memory (LSTM) architecture to model the temporal relationship between observations at different time-steps by tasking the LSTM memory with the extraction of significant features of the hidden portion of the MDP’s states. We show that modeling a PRNG with a partially observable MDP and an LSTM architecture largely improves the results of the fully observable feedforward RL approach introduced in previous work.

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Random Number Generator with Long-Range Dependence and Multifractal Behavior Based on Memristor

Electronics ◽

10.3390/electronics9101607 ◽

2020 ◽

Vol 9 (10) ◽

pp. 1607 ◽

Cited By ~ 1

Author(s):

María Téllez ◽

Johan Mejía ◽

Hans López ◽

Cesar Hernández

Keyword(s):

Long Range ◽

Random Number ◽

System Modeling ◽

Random Number Generator ◽

Random Number Generation ◽

Long Range Dependence ◽

Hurst Parameter ◽

Number Generator ◽

Behavior Based ◽

Multifractal Behavior

Random number generators are used in areas such as encryption and system modeling, where some of these exhibit fractal behaviors. For this reason, it is interesting to make use of the memristor characteristics for the random number generation. Accordingly, the objective of this article is to evaluate the performance of a chaotic memristive system as a random number generator with fractal behavior and long-range dependence. To achieve the above, modeling memristor and its corresponding chaotic systems is performed, from which a random number generator is constructed. Subsequently, the Hurst parameter for the detection of long-range dependence is estimated and a fractal analysis of the synthesized data is performed. Finally, a comparison between the model proposed in the research and the β-MWM algorithm is made. The results obtained show that the data synthesized from the proposed generator have a variable Hurst parameter and both monofractal and multifractal behavior. The main contribution of this research is the proposal of a new model for the synthesis of traces with long-range dependence and fractal behavior based on the non-linearity of the memristor.

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