ANALOG/MIXED-SIGNAL CIRCUIT VERIFICATION USING MODELS GENERATED FROM SIMULATION TRACES

2010 ◽  
Vol 21 (02) ◽  
pp. 191-210 ◽  
Author(s):  
SCOTT LITTLE ◽  
DAVID WALTER ◽  
KEVIN JONES ◽  
CHRIS MYERS ◽  
ALPER SEN
Keyword(s):  
Formal Verification ◽  
Phase Detector ◽  
System Level ◽  
Switched Capacitor ◽  
Levels Of Abstraction ◽  
Mixed Signal ◽  
Circuit Verification ◽  
System Level Simulation

Verification of analog/mixed-signal (AMS) circuits is complicated by the difficulty of obtaining circuit models at suitable levels of abstraction. We propose a method to automatically generate abstract models suitable for formal verification and system-level simulation from transistor-level simulation traces. This paper discusses the application of the proposed methodology to a switched capacitor integrator and PLL phase detector.

scholarly journals System Level Simulation of Microgrid Power Electronic Systems

Electronics ◽  
2021 ◽  
Vol 10 (6) ◽  
pp. 644
Author(s):  
Michal Frivaldsky ◽  
Jan Morgos ◽  
Michal Prazenica ◽  
Kristian Takacs
Keyword(s):  
Smart Grid ◽  
Simulation Model ◽  
Real Time ◽  
Power Converter ◽  
System Level ◽  
Time Behavior ◽  
Operational Parameters ◽  
System Level Simulation ◽  
Time Operation ◽  
The Impact

In this paper, we describe a procedure for designing an accurate simulation model using a price-wised linear approach referred to as the power semiconductor converters of a DC microgrid concept. Initially, the selection of topologies of individual power stage blocs are identified. Due to the requirements for verifying the accuracy of the simulation model, physical samples of power converters are realized with a power ratio of 1:10. The focus was on optimization of operational parameters such as real-time behavior (variable waveforms within a time domain), efficiency, and the voltage/current ripples. The approach was compared to real-time operation and efficiency performance was evaluated showing the accuracy and suitability of the presented approach. The results show the potential for developing complex smart grid simulation models, with a high level of accuracy, and thus the possibility to investigate various operational scenarios and the impact of power converter characteristics on the performance of a smart gird. Two possible operational scenarios of the proposed smart grid concept are evaluated and demonstrate that an accurate hardware-in-the-loop (HIL) system can be designed.

scholarly journals Gem5-X

2021 ◽  
Vol 18 (4) ◽  
pp. 1-27
Author(s):  
Yasir Mahmood Qureshi ◽  
William Andrew Simon ◽  
Marina Zapater ◽  
Katzalin Olcoz ◽  
David Atienza
Keyword(s):  
Visual Recognition ◽  
Energy Savings ◽  
Video Encoding ◽  
System Level ◽  
Heterogeneous Architecture ◽  
Video Analytics ◽  
Smart Systems ◽  
System Level Simulation ◽  
Many Core ◽  
New Applications

The increasing adoption of smart systems in our daily life has led to the development of new applications with varying performance and energy constraints, and suitable computing architectures need to be developed for these new applications. In this article, we present gem5-X, a system-level simulation framework, based on gem-5, for architectural exploration of heterogeneous many-core systems. To demonstrate the capabilities of gem5-X, real-time video analytics is used as a case-study. It is composed of two kernels, namely, video encoding and image classification using convolutional neural networks (CNNs). First, we explore through gem5-X the benefits of latest 3D high bandwidth memory (HBM2) in different architectural configurations. Then, using a two-step exploration methodology, we develop a new optimized clustered-heterogeneous architecture with HBM2 in gem5-X for video analytics application. In this proposed clustered-heterogeneous architecture, ARMv8 in-order cluster with in-cache computing engine executes the video encoding kernel, giving 20% performance and 54% energy benefits compared to baseline ARM in-order and Out-of-Order systems, respectively. Furthermore, thanks to gem5-X, we conclude that ARM Out-of-Order clusters with HBM2 are the best choice to run visual recognition using CNNs, as they outperform DDR4-based system by up to 30% both in terms of performance and energy savings.

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