FOUR QUADRANT ANALOG MULTIPLIER USING DUAL-CURRENT-CONTROLLED CURRENT DIFFERENCING BUFFERED AMPLIFIER

2011 ◽  
Vol 20 (02) ◽  
pp. 223-231 ◽  
Author(s):  
ABHIRUP LAHIRI ◽  
ANKUSH CHOWDHURY

A novel four quadrant analog multiplier (FQAM) is presented using the recently proposed active building block (ABB), namely the dual-current-controlled current differencing buffered amplifier (DCC-CDBA). The inputs to the circuit are two bipolar current signals and current and voltage outputs are available as multiplication of the input signals. The use of DCC-CDBA in four quadrant multiplier design is attractive, since the circuit structure is very simple and uses reduced number of components, viz. only one DCC-CDBA, which is constructed using two second-generation current controlled conveyors (CCCIIs). The circuit operation is current-tunable and ideally temperature insensitive. The workability of the circuit is verified using PSPICE simulations.

2012 ◽  
Vol 2012 ◽  
pp. 1-7 ◽  
Author(s):  
Rajeshwari Pandey ◽  
Neeta Pandey ◽  
B. Sriram ◽  
Sajal K. Paul

This paper presents an analog multiplier using single operational transresistance amplifier (OTRA). The proposed circuit is suitable for integration as it does not use any external passive component. It can be used as a four-quadrant multiplier. Theoretical propositions are verified through PSPICE simulations using 0.5 μm CMOS parameters provided by MOSIS (AGILENT). The simulation results are in close agreement with theoretical predictions. The workability of the proposed multiplier is also tested through two applications, namely, a squarer and an amplitude modulator.


2020 ◽  
Vol 15 (3) ◽  
pp. 1-12
Author(s):  
Ana Isabela Araújo Cunha ◽  
Antonio José Sobrinho De Sousa ◽  
Edson Pinto Santana ◽  
Robson Nunes De Lima ◽  
Fabian Souza De Andrade ◽  
...  

This work presents a CMOS four quadrant analog multiplier architecture for application as the synapse element in analog cellular neural networks. For this reason, the circuit has voltage-mode inputs and a current-mode output and the chief design targets are compactness and low energy consumption. A signal application method is proposed that avoids voltage reference generators, which contributes to reduce sensitivity to supply voltage variation. Performance analysis through simulation has been accomplished for a design in CMOS 130 nm technology with 163 µm2 total active area. The circuit features ±50 mV input voltage range, 86 µW static power and ‑28.4 dB maximum total harmonic distortion. A simple technique for manual calibration is also presented.


1985 ◽  
Author(s):  
Klaas Bult ◽  
Hans Wallinga

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