Design and Verification of New n-Bit Quantum-Dot Synchronous Counters Using Majority Function-Based JK Flip-Flops

Quantum-dot Cellular Automata (QCA) is an attractive nanoelectronics paradigm which is widely advocated as a possible replacement of conventional CMOS technology. Designing memory cells is a very interesting field of research in QCA domain. In this paper, we are going to propose novel nanotechnology-compatible designs based on the majority gate structures. In the first step, this objective is accomplished by QCA implementation of two well-organized JK flip-flop designs and in the second step; synchronous counters with different sizes are presented as an application. To evaluate functional correctness of the proposed designs and compare with state-of-the-art, QCADesigner tool is employed.

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Towards the Design of Cost-efficient Generic Register Using Quantum-dot Cellular Automata

Nanoscience &Nanotechnology-Asia ◽

10.2174/2210681209666190412142207 ◽

2020 ◽

Vol 10 (4) ◽

pp. 534-547

Author(s):

Chiradeep Mukherjee ◽

Saradindu Panda ◽

Asish K. Mukhopadhyay ◽

Bansibadan Maji

Keyword(s):

Cellular Automata ◽

Quantum Dot ◽

Power Dissipation ◽

Cmos Technology ◽

Oxide Semiconductor ◽

Digital Data ◽

Design Parameters ◽

Flip Flop ◽

Quantum Dot Cellular Automata ◽

Cost Efficient

Background: The advancement of VLSI in the application of emerging nanotechnology explores quantum-dot cellular automata (QCA) which has got wide acceptance owing to its ultra-high operating speed, extremely low power dissipation with a considerable reduction in feature size. The QCA architectures are emerging as a potential alternative to the conventional complementary metal oxide semiconductor (CMOS) technology. Experimental: Since the register unit has a crucial role in digital data transfer between the electronic devices, such study leading to the design of cost-efficient and highly reliable QCA register is expected to be a prudent area of research. A thorough survey on the existing literature shows that the generic models of Serial-in Serial Out (SISO), Serial-in-Parallel-Out (SIPO), Parallel-In- Serial-Out (PISO) and Parallel-in-Parallel-Out (PIPO) registers are inadequate in terms of design parameters like effective area, delay, O-Cost, Costα, etc. Results: This work introduces a layered T gate for the design of the D flip flop (LTD unit), which can be broadly used in SISO, SIPO, PISO, and PIPO register designs. For detection and reporting of high susceptible errors and defects at the nanoscale, the reliability and defect tolerant analysis of LTD unit are also carried out in this work. The QCA design metrics for the general register layouts using LTD unit is modeled. Conclusion: Moreover, the cost metrics for the proposed LTD layouts are thoroughly studied to check the functional complexity, fabrication difficulty and irreversible power dissipation of QCA register layouts.

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Design of Efficient Full Adder in Quantum-Dot Cellular Automata

The Scientific World JOURNAL ◽

10.1155/2013/250802 ◽

2013 ◽

Vol 2013 ◽

pp. 1-10 ◽

Cited By ~ 36

Author(s):

Bibhash Sen ◽

Ayush Rajoria ◽

Biplab K. Sikdar

Keyword(s):

Cellular Automata ◽

Quantum Dot ◽

Full Adder ◽

Cmos Technology ◽

Digital Design ◽

Majority Gate ◽

Feature Size ◽

Quantum Dot Cellular Automata ◽

Potential Alternative ◽

High Level

Further downscaling of CMOS technology becomes challenging as it faces limitation of feature size reduction. Quantum-dot cellular automata (QCA), a potential alternative to CMOS, promises efficient digital design at nanoscale. Investigations on the reduction of QCA primitives (majority gates and inverters) for various adders are limited, and very few designs exist for reference. As a result, design of adders under QCA framework is gaining its importance in recent research. This work targets developing multi-layered full adder architecture in QCA framework based on five-input majority gate proposed here. A minimum clock zone (2 clock) with high compaction (0.01 μm2) for a full adder around QCA is achieved. Further, the usefulness of such design is established with the synthesis of high-level logic. Experimental results illustrate the significant improvements in design level in terms of circuit area, cell count, and clock compared to that of conventional design approaches.

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Design of a New Multiplexer Structure Based on a New Fault-Tolerant Majority Gate in Quantum-Dot Cellular Automata

10.21203/rs.3.rs-355476/v1 ◽

2021 ◽

Author(s):

Yaser Rahmani ◽

Saeed Rasouli Heikalabad ◽

Mohammad Mosleh

Keyword(s):

Fault Tolerance ◽

Cellular Automata ◽

Quantum Dot ◽

High Performance ◽

Fault Tolerant ◽

Cmos Technology ◽

Good Alternative ◽

Majority Gate ◽

Power Efficient ◽

Quantum Dot Cellular Automata

Abstract Quantum-dot Cellular Automata (QCA) technology is believed to be a good alternative to CMOS technology. This nanoscale technology can provide a platform for design and implementation of high performance and power efficient logic circuits. However, the fabrication of QCA circuits is susceptible to faults appearing in this form of missing cells, additional cells, rotated cells, and displaced cells. Over the years, several solutions have been proposed to address these problems. This paper presents a new solution for improving the fault tolerance of three input majority gate. The proposed majority gate is then used to design 2-1 multiplexer and 4-1 multiplexer. The proposed designs are implemented in QCA Designer. Simulation results demonstrate significant improvements in terms of fault tolerance and area requirement.

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