Design of a New Multiplexer Structure Based on a New Fault-Tolerant Majority Gate in Quantum-Dot Cellular Automata

2021 ◽  
Author(s):  
Yaser Rahmani ◽  
Saeed Rasouli Heikalabad ◽  
Mohammad Mosleh
Keyword(s):  
Fault Tolerance ◽  
Cellular Automata ◽  
Quantum Dot ◽  
High Performance ◽  
Fault Tolerant ◽  
Cmos Technology ◽  
Good Alternative ◽  
Majority Gate ◽  
Power Efficient ◽  
Quantum Dot Cellular Automata

Abstract Quantum-dot Cellular Automata (QCA) technology is believed to be a good alternative to CMOS technology. This nanoscale technology can provide a platform for design and implementation of high performance and power efficient logic circuits. However, the fabrication of QCA circuits is susceptible to faults appearing in this form of missing cells, additional cells, rotated cells, and displaced cells. Over the years, several solutions have been proposed to address these problems. This paper presents a new solution for improving the fault tolerance of three input majority gate. The proposed majority gate is then used to design 2-1 multiplexer and 4-1 multiplexer. The proposed designs are implemented in QCA Designer. Simulation results demonstrate significant improvements in terms of fault tolerance and area requirement.

scholarly journals Novel Design for Quantum Dots Cellular Automata to Obtain Fault-Tolerant Majority Gate

2012 ◽  
Vol 2012 ◽  
pp. 1-7 ◽  
Author(s):  
Razieh Farazkish ◽  
Samira Sayedsalehi ◽  
Keivan Navi
Keyword(s):  
Fault Tolerance ◽  
Cellular Automata ◽  
Fault Tolerant ◽  
Electrostatic Energy ◽  
Majority Gate ◽  
Quantum Dot Cellular Automata ◽  
Dislocation Cells ◽  
The Difference ◽  
Qca Circuits ◽  
Novel Design

Quantum-dot Cellular Automata (QCA) is one of the most attractive technologies for computing at nanoscale. The principle element in QCA is majority gate. In this paper, fault-tolerance properties of the majority gate is analyzed. This component is suitable for designing fault-tolerant QCA circuits. We analyze fault-tolerance properties of three-input majority gate in terms of misalignment, missing, and dislocation cells. In order to verify the functionality of the proposed component some physical proofs using kink energy (the difference in electrostatic energy between the two polarization states) and computer simulations using QCA Designer tool are provided. Our results clearly demonstrate that the redundant version of the majority gate is more robust than the standard style for this gate.

scholarly journals Design and Analysis of Fault-Tolerant 1:2 Demultiplexer Using Quantum-Dot Cellular Automata Nano-Technology

Electronics ◽  
2021 ◽  
Vol 10 (21) ◽  
pp. 2565
Author(s):  
Saeid Seyedi ◽  
Nima Jafari Navimipour ◽  
Akira Otsuki
Keyword(s):  
Fault Tolerance ◽  
Cellular Automata ◽  
Quantum Dot ◽  
Fault Tolerant ◽  
Nano Technology ◽  
Ultra Low Power ◽  
Quantum Dot Cellular Automata ◽  
Whole Process ◽  
Dislocation Cells ◽  
Rapid Switching

Quantum-dot Cellular Automata (QCA) is an innovative paradigm bringing hopeful applications in the perceptually novel computing layout in quantum electronics. The circuits manufactured by QCA technology can provide a notable decrease in size, rapid-switching velocity, and ultra-low power utilization. The demultiplexer is a beneficial component to optimize the whole process in any logical design, and therefore is very important in QCA. Moreover, fault-tolerant circuits can improve the reliability of digital circuits by redundancy. Hence, the present investigation illustrates a novel QCA-based fault-tolerant 1:2 demultiplexer construct that employs a two-input AND gate and inverter. The functionality of the suggested layout was executed and evaluated with the utilization of the QCADesigner 2.0.3 simulator. This paper utilizes cell redundancy on the wire, inverter, and AND gates for designing a fault-tolerant demultiplexer. Four components (i.e., missing cells, dislocation cells, extra cells, and misalignment) were analyzed by the QCADesigner simulator. The simulation results demonstrated that our proposed QCA-based fault-tolerant 1:2 demultiplexer acted more efficiently than prior constructs regarding delay and fault tolerance. The proposed fault-tolerant 1:2 demultiplexer could attain high fault-tolerance when single missing cell or extra cell faults exist in the QCA layout.

scholarly journals Design of Efficient Full Adder in Quantum-Dot Cellular Automata

2013 ◽  
Vol 2013 ◽  
pp. 1-10 ◽  
Author(s):  
Bibhash Sen ◽  
Ayush Rajoria ◽  
Biplab K. Sikdar
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Full Adder ◽  
Cmos Technology ◽  
Digital Design ◽  
Majority Gate ◽  
Feature Size ◽  
Quantum Dot Cellular Automata ◽  
Potential Alternative ◽  
High Level

Further downscaling of CMOS technology becomes challenging as it faces limitation of feature size reduction. Quantum-dot cellular automata (QCA), a potential alternative to CMOS, promises efficient digital design at nanoscale. Investigations on the reduction of QCA primitives (majority gates and inverters) for various adders are limited, and very few designs exist for reference. As a result, design of adders under QCA framework is gaining its importance in recent research. This work targets developing multi-layered full adder architecture in QCA framework based on five-input majority gate proposed here. A minimum clock zone (2 clock) with high compaction (0.01 μm2) for a full adder around QCA is achieved. Further, the usefulness of such design is established with the synthesis of high-level logic. Experimental results illustrate the significant improvements in design level in terms of circuit area, cell count, and clock compared to that of conventional design approaches.

Design and analysis of new fault-tolerant majority gate for quantum-dot cellular automata

2016 ◽  
Vol 15 (4) ◽  
pp. 1484-1497 ◽  
Author(s):  
Huakun Du ◽  
Hongjun Lv ◽  
Yongqiang Zhang ◽  
Fei Peng ◽  
Guangjun Xie
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Fault Tolerant ◽  
Majority Gate ◽  
Quantum Dot Cellular Automata

An Area and Energy Efficient RAM Cell Design in Quantum Dot Cellular Automata

2019 ◽  
Vol 16 (10) ◽  
pp. 4179-4187
Author(s):  
Amanpreet Sandhu ◽  
Sheifali Gupta
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
High Performance ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Short Channel Effects ◽  
Short Channel ◽  
Quantum Dot Cellular Automata ◽  
Channel Effects

The Conventional Complementary Metal oxide semiconductor (CMOS) technology has been revolutionized from the past few decades. However, the CMOS circuit faces serious constraints like short channel effects, quantum effects, doping fluctuations at the nanoscale which limits them to further scaling down at nano meter range. Among various existing nanotechnologies, Quantum dot Cellular Automata (QCA) provides new solution at nanocircuit design. The technical advancement of the paper lies in designing a high performance RAM cell with less QCA cells, less occupational area and lower power dissipation characteristics. The design occupies 12.5% lower area, 16.6% lower input to output delay, and dissipates 18.26% lesser energy than the designs in the literature. The proposed RAMcell is robust due to lesser noise variations. Also it has less fabrication cost due to absence of rotated cells.

Design of quantum dot cellular automata based fault tolerant convolution encoders for secure nanocomputing

2020 ◽  
Vol 18 (06) ◽  
pp. 2050032
Author(s):  
Suhaib Ahmed ◽  
Syed Farah Naz
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Communication Networks ◽  
Data Transfer ◽  
Fault Tolerant ◽  
Satellite Communications ◽  
Cmos Technology ◽  
Ultra Low Power ◽  
Quantum Dot Cellular Automata ◽  
Cost Efficient

The issues faced by Complementary metal oxide semi-conductor (CMOS) technology in the nanoregime have led to the research of other possible technologies which can operate with same functionalities however, with higher speed and lower power dissipation. One such technology is Quantum-dot Cellular Automata (QCA). At present, logic circuit designs using QCA have been comprehensively researched and one such application area being investigated is data transmission. Various data transfer techniques for reliable data transfer are available and among them convolution coding is being widely used in mobile, radio and satellite communications. Considering the evolution towards nano communication networks, in this paper an ultra-proficient designs of 1/2 rate and 1/3 rate convolution encoders based on a cost-efficient and fault tolerant XOR gate design have been proposed for application in nano communication networks. Based on the performance analysis, it is observed that the proposed designs are efficient in respect to cell count, area, delay and circuit cost and achieves performance improvement up to 40.21% for 1/2 encoder and 31.81% for 1/3 encoder compared to the best design in the literature. In addition to this, the energy dissipation analysis of the proposed designs is also presented. The proposed designs can thus be efficiently utilized in various nanocommunication applications requiring minimal area and ultra-low power consumption.

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