Low Complexity Parallel FIR Filter Circuit Design by Exploiting Signal Correlation in Multimedia Applications

An ultra-low power, portable, and easily implemented Holter recorder is necessary for patients or researchers of electrocardiogram (ECG). Such a Holter recorder with off-the-shelf components is realized with mixed signal processor (MSP) in this paper. To decrease the complexity of analog circuits and the interference of 60 Hz noise from power line, we use the MSP to implement a finite impulse response (FIR) filter which is equiripple design. We also integrate the ring buffer for the input samples and the symmetrical characteristic of the FIR filter for efficiently computing convolution. The experimental results show that the ECG output signal with the PQRST feature is easy to be distinguished. This ECG signal is recorded for 24 hours using a SD card. Furthermore, the ECG signal is transmitted with a smartphone via Bluetooth to decrease the burden of the Holter recorder. As a result, this paper uses the Lomb method for the spectral analysis of Heart Rate Variability (HRV) better than Fast Fourier Transform (FFT).

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Matrix Decomposition Based Low-Complexity FIR Filter: Further Results

2020 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas45731.2020.9180522 ◽

2020 ◽

Author(s):

Hao Wang ◽

Zhijin Zhao ◽

Li Zhao

Keyword(s):

Matrix Decomposition ◽

Low Complexity ◽

Fir Filter

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Novel reconfigurable architecture with low complexity FIR filter

International Conference on Pattern Recognition, Informatics and Medical Engineering (PRIME-2012) ◽

10.1109/icprime.2012.6208303 ◽

2012 ◽

Cited By ~ 1

Author(s):

K. Sagadevan ◽

V. Babu ◽

S. Arivumani Samson

Keyword(s):

Low Complexity ◽

Fir Filter ◽

Reconfigurable Architecture

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Design and implementation of low complexity circularly symmetric 2D FIR filter architectures

Multidimensional Systems and Signal Processing ◽

10.1007/s11045-020-00714-3 ◽

2020 ◽

Vol 31 (4) ◽

pp. 1385-1410

Author(s):

Venkata Krishna Odugu ◽

C. Venkata Narasimhulu ◽

K. Satya Prasad

Keyword(s):

Low Complexity ◽

Fir Filter ◽

Design And Implementation

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Efficient FIR Filter Architecture using FPGA

Recent Advances in Computer Science and Communications ◽

10.2174/2213275912666190603115506 ◽

2020 ◽

Vol 13 (1) ◽

pp. 91-98

Author(s):

Ahmed K. Jameil ◽

Yassir A. Ahmed ◽

Saad Albawi

Keyword(s):

Low Power ◽

Communication Systems ◽

High Performance ◽

Finite Impulse Response ◽

Low Complexity ◽

Fir Filter ◽

Fir Filters ◽

Filter Architecture ◽

Circuit Techniques ◽

And Performance

Background: Advance communication systems require new techniques for FIR filters with resource efficiency in terms of high performance and low power consumption. Lowcomplexity architectures are required by FIR filters for implementation in field programmable gate Arrays (FPGA). In addition, FIR filters in multistandard wireless communication systems must have low complexity and be reconfigurable. The coefficient multipliers of FIR filters are complicated. Objective: The implementation and application of high tap FIR filters by a partial product reduce this complexity. Thus, this article proposes a novel digital finite impulse response (FIR) filter architecture with FPGA. Method: The proposed technique FIR filter is based on a new architecture method and implemented using the Quartus II design suite manufactured by Altera. Also, the proposed architecture is coded in Verilog HDL and the code developed from the proposed architecture has been simulated using Modelsim. This efficient FIR filter architecture is based on the shift and add method. Efficient circuit techniques are used to further improve power and performance. In addition, the proposed architecture achieves better hardware requirements as multipliers are reduced. A 10-tap FIR filter is implemented on the proposed architecture. Results: The design’s example demonstrates a 25% reduction in resource usage compared to existing reconfigurable architectures with FPGA synthesis. In addition, the speed of the proposed architecture is 37% faster than the best performance of existing methods. Conclusion: The proposed architecture offers low power and improved speed with the lowcomplexity design that gives the best architecture FIR filter for both reconfigurable and fixed applications.

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