Impact of Dot-Size and Dot-Location Variations on Capacitance–Voltage Characteristics and Flat-Band Voltage Shift of Quantum-Dot Non-Volatile Memory Cells

2011 ◽  
Vol 50 (4) ◽  
pp. 044301
Author(s):  
Yasuhisa Omura ◽  
Yuta Horikawa
2020 ◽  
Vol 13 (11) ◽  
pp. 111006
Author(s):  
Li-Chuan Sun ◽  
Chih-Yang Lin ◽  
Po-Hsun Chen ◽  
Tsung-Ming Tsai ◽  
Kuan-Ju Zhou ◽  
...  

2020 ◽  
Vol 29 (01n04) ◽  
pp. 2040001
Author(s):  
N. R. Butterfield ◽  
R. Mays ◽  
B. Khan ◽  
R. Gudlavalleti ◽  
F. C. Jain

This paper presents the theory, fabrication and experimental testing results for a multiple state Non-Volatile Memory (NVM), comprised of hafnium oxide high-k dielectric tunnel and gate barriers as well as a Silicon Quantum Dot Superlattice (QDSL) implemented for the floating gate and inversion channel (QDG) and (QDC) respectively. With the conclusion of Moore’s Law for conventional transistor fabrication, regarding the minimum gate size, current efforts in memory cell research and development are focused on bridging the gap between the conventions of the past sixty years and the future of computing. One method of continuing the increasing chip density is to create multistate devices capable of storing and processing additional logic states beyond 1 and 0. Replacing the silicon nitride floating gate of a conventional Flash NVM with QDSL gives rise to minibands that result in greater control over charge levels stored in the QDG and additional intermediate states. Utilizing Hot Carrier Injection (HCI) programming, for the realized device, various magnitudes of gate voltage pulses demonstrated the ability to accurately control the charge levels stored in the QDG. This corresponds to multiple threshold voltage shifts allowing detection of multiple states during read operations.


2017 ◽  
Vol 7 (1) ◽  
Author(s):  
Sung Heo ◽  
Hyoungsun Park ◽  
Dong-Su Ko ◽  
Yong Su Kim ◽  
Yong Koo Kyoung ◽  
...  

1998 ◽  
Vol 510 ◽  
Author(s):  
K. Vanheusden ◽  
W.L. Warren ◽  
D.M. Fleetwood ◽  
R.A.B. Devine ◽  
B.L. Draper ◽  
...  

AbstractEver since the introduction of the metal-oxide-silicon field-effect-transistor (MOSFET), the nature of mobile and trapped charge in the oxide layer has been studied in great detail. For example, contamination with alkali ions such as sodium, causing instability of the flat-band voltage, was a major concern in the early days of MOS fabrication. Another SiO2 impurity of particular interest is hydrogen, because of its beneficial property of passivating charge traps. In this work we show that annealing of Si/SiO2/Si structures in forming gas (Ar:H2; 95:5) above 400 °C can introduce mobile H+ ions into the SiO2 layer. These mobile protons are confined within the oxide layer, and their space-charge distribution is well controllable and easily rearrangeable by applying a gate bias, making them potentially useful for application in a reliable nonvolatile MOSFET memory device. We present speed, retention, endurance, and radiation tolerance data showing that this non-volatile memory technology can be competitive with existing Si-based non-volatile memory technologies such as Flash.The chemical kinetics of mobile-proton reactions in the SiO2 film are also analyzed in greater detail. Our data show that the initial buildup of mobile protons during hydrogen annealing is limited by the rate of lateral hydrogen diffusion into the buried SiO2 films. The final density of mobile protons is determined by the cooling rate which terminates the annealing process and, in the case of subsequent anneals, by the temperature of the final anneal. To explain the observations, we propose a dynamical equilibrium model. Based on these insights, the incorporation of the proton generation process into standard semiconductor process flows is discussed.


Author(s):  
Antoine Jalabert ◽  
Amara Amara ◽  
Fabien Clermidy

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