Quantum Dot Floating Gate Transistor with Multi-wall Carbon Nano Tube Channel for Non-volatile Memory Devices

Author(s):  
Rajeswari Joga
2020 ◽  
Vol 29 (01n04) ◽  
pp. 2040001
Author(s):  
N. R. Butterfield ◽  
R. Mays ◽  
B. Khan ◽  
R. Gudlavalleti ◽  
F. C. Jain

This paper presents the theory, fabrication and experimental testing results for a multiple state Non-Volatile Memory (NVM), comprised of hafnium oxide high-k dielectric tunnel and gate barriers as well as a Silicon Quantum Dot Superlattice (QDSL) implemented for the floating gate and inversion channel (QDG) and (QDC) respectively. With the conclusion of Moore’s Law for conventional transistor fabrication, regarding the minimum gate size, current efforts in memory cell research and development are focused on bridging the gap between the conventions of the past sixty years and the future of computing. One method of continuing the increasing chip density is to create multistate devices capable of storing and processing additional logic states beyond 1 and 0. Replacing the silicon nitride floating gate of a conventional Flash NVM with QDSL gives rise to minibands that result in greater control over charge levels stored in the QDG and additional intermediate states. Utilizing Hot Carrier Injection (HCI) programming, for the realized device, various magnitudes of gate voltage pulses demonstrated the ability to accurately control the charge levels stored in the QDG. This corresponds to multiple threshold voltage shifts allowing detection of multiple states during read operations.


2013 ◽  
Vol 1527 ◽  
Author(s):  
Rudra S. Dhar ◽  
St.J. Dixon-Warren ◽  
Mohamed A. Kawaliye ◽  
Jeff Campbell ◽  
Mike Green ◽  
...  

ABSTRACTThis report outlines a methodology for reading back different electrical charges, from Non Volatile Memory (NVM) based Flash devices. The charge is stored in the floating gates (FGs) of the transistors. Reading back these charges in the form of logic levels of “1 bit (1b)” and “0 bit (0b)” without deleting the information from the device was the goal. Scanning Capacitance Microscopy (SCM) with ∼50-100 nm spatial resolution was used, to directly probe the charge on Floating Gate Transistor (FGT) channels. Transistor charge values (ON/OFF or “1b/0b”) are measured. Both the sample preparation and SCM probing methods are discussed. The application has been demonstrated with SanDisk based 64 MB NAND Flash memory device.


2020 ◽  
Vol 33 (2) ◽  
pp. 155-167
Author(s):  
Renu Rajput ◽  
Rakesh Vaid

Traditional flash memory devices consist of Polysilicon Control Gate (CG) - Oxide-Nitride-Oxide (ONO - Interpoly Dielectric) - Polysilicon Floating Gate (FG) - Silicon Oxide (Tunnel dielectric) - Substrate. The dielectrics have to be scaled down considerably in order to meet the escalating demand for lower write/erase voltages and higher density of cells. But as the floating gate dimensions are scaled down the charge stored in the floating gate leak out more easily via thin tunneling oxide below the floating gate which causes serious reliability issues and the whole amount of stored charge carrying information can be lost. The possible route to eliminate this problem is to use high-k based interpoly dielectric and to replace the polysilicon floating gate with a metal floating gate. At larger physical thickness, these materials have similar capacitance value hence avoiding tunneling effect. Discrete nanocrystal memory has also been proposed to solve this problem. Due to its high operation speed, excellent scalability and higher reliability it has been shown as a promising candidate for future non-volatile memory applications. This review paper focuses on the recent efforts and research activities related to the fabrication and characterization of non-volatile memory device with metal floating gate/metal nanocrystals as the charge storage layer.


2016 ◽  
Vol 4 (46) ◽  
pp. 10967-10972 ◽  
Author(s):  
Sujaya Kumar Vishwanath ◽  
Jihoon Kim

The all-solution-based memory devices demonstrated excellent bipolar switching behavior with a high resistive switching ratio of 103, excellent endurance of more than 1000 cycles, stable retention time greater than 104s at elevated temperatures, and fast programming speed of 250 ns.


2020 ◽  
Vol 78 ◽  
pp. 105584 ◽  
Author(s):  
Jia-Qin Yang ◽  
Li-Yu Ting ◽  
Ruopeng Wang ◽  
Jing-Yu Mao ◽  
Yi Ren ◽  
...  

AIP Advances ◽  
2020 ◽  
Vol 10 (2) ◽  
pp. 025111 ◽  
Author(s):  
Divya Kaushik ◽  
Utkarsh Singh ◽  
Upasana Sahu ◽  
Indu Sreedevi ◽  
Debanjan Bhowmik

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