Energy/area/delay trade-offs in the physical design of on-chip segmented bus architecture

2006 ◽  
Author(s):  
Jin Guo ◽  
Antonis Papanikolaou ◽  
Pol Marchal ◽  
Francky Catthoor
Keyword(s):  
Physical Design ◽  
Trade Offs ◽  
On Chip ◽  
Bus Architecture

Serial-Link Bus: A Low-Power On-Chip Bus Architecture

2009 ◽  
Vol 56 (9) ◽  
pp. 2020-2032 ◽  
Author(s):  
M. Ghoneima ◽  
Y. Ismail ◽  
M.M. Khellah ◽  
J. Tschanz ◽  
V. De
Keyword(s):  
Low Power ◽  
Serial Link ◽  
On Chip ◽  
Bus Architecture

scholarly journals Design Trade-offs in Customized On-chip Crossbar Schedulers

2008 ◽  
Vol 58 (1) ◽  
pp. 69-85 ◽  
Author(s):  
Jae Young Hur ◽  
Stephan Wong ◽  
Todor Stefanov
Keyword(s):  
Trade Offs ◽  
On Chip

A Phase-Based Approach for On-Chip Bus Architecture Optimization

2008 ◽  
Vol 52 (6) ◽  
pp. 626-645 ◽  
Author(s):  
J. Lee ◽  
H.-J. Lee ◽  
C. Lee
Keyword(s):  
On Chip ◽  
Bus Architecture ◽  
Architecture Optimization

scholarly journals An Effective on-Chip Network Topology for Network on Chip (Noc) Trade-Offs

2016 ◽  
Vol 9 (17) ◽  
Author(s):  
M. Venkateswara Rao ◽  
T. V. Rama Krishna ◽  
S. Raaga Sai Sruthi ◽  
S. Akhila ◽  
Y. Gopi ◽  
...  
Keyword(s):  
Network Topology ◽  
Network On Chip ◽  
Trade Offs ◽  
On Chip
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