scholarly journals Design Trade-offs in Customized On-chip Crossbar Schedulers

2008 ◽  
Vol 58 (1) ◽  
pp. 69-85 ◽  
Author(s):  
Jae Young Hur ◽  
Stephan Wong ◽  
Todor Stefanov
Keyword(s):  
Trade Offs ◽  
On Chip

scholarly journals An Effective on-Chip Network Topology for Network on Chip (Noc) Trade-Offs

2016 ◽  
Vol 9 (17) ◽  
Author(s):  
M. Venkateswara Rao ◽  
T. V. Rama Krishna ◽  
S. Raaga Sai Sruthi ◽  
S. Akhila ◽  
Y. Gopi ◽  
...  
Keyword(s):  
Network Topology ◽  
Network On Chip ◽  
Trade Offs ◽  
On Chip

Trade-offs in the design of a router with both guaranteed and best-effort services for networks on chip

2003 ◽  
Vol 150 (5) ◽  
pp. 294 ◽  
Author(s):  
E. Rijpkema ◽  
K. Goossens ◽  
A. Rdulescu ◽  
J. Dielissen ◽  
J. van Meerbergen ◽  
...  
Keyword(s):  
Best Effort ◽  
Networks On Chip ◽  
Trade Offs ◽  
On Chip

scholarly journals A New Router Architecture for High-Performance Intrachip Networks

2008 ◽  
Vol 3 (1) ◽  
pp. 23-31
Author(s):  
Everton Carara ◽  
Ney Calazans ◽  
Fernando Moraes
Keyword(s):  
High Performance ◽  
Packet Switching ◽  
Circuit Switching ◽  
Transmission Method ◽  
Communication Architecture ◽  
Virtual Channels ◽  
Trade Offs ◽  
Communication Architectures ◽  
Session Layer ◽  
On Chip

For almost a decade now, Network on Chip (NoC) concepts have evolved to provide an interesting alternative to more traditional intrachip communication architectures (e.g. shared busses) for the design of complex Systems on Chip (SoCs). A considerable number of NoC proposals are available, focusing on different sets of optimization aspects, related to specific classes of applications. Each such application employs a NoC as part of its underlying implementation infrastructure. Many of the mentioned optimization aspects target results such as Quality of Service (QoS) achievement and/or power consumption reduction. On the other hand, the use of NoCs brings about the solution of new design problems, such to the choice of synchronization method to employ between NoC routers and application modules mapping. Although the availability of NoC structures is already rather ample, some design choices are at base of many, if not most, NoC proposals. These include the use of wormhole packet switching and virtual channels. This work pledges against this practice. It discusses trade-offs of using circuit or packet switching, arguing in favor the use of the former with fixed size packets (cells). Quantitative data supports the argumentation. Also, the work proposes and justifies replacing the use of virtual channels by replicated channels, based on the abundance of wires in current and expected deep sub-micron technologies. Finally, the work proposes a transmission method coupling the use of session layer structures to circuit switching to better support application implementation. The main reported result is the availability of a router with reduced latency and area, a communication architecture adapted for high-performance applications.

Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures

2005 ◽  
Vol 54 (8) ◽  
pp. 1025-1040 ◽  
Author(s):  
P.P. Pande ◽  
C. Grecu ◽  
M. Jones ◽  
A. Ivanov ◽  
R. Saleh
Keyword(s):  
Performance Evaluation ◽  
Network On Chip ◽  
Trade Offs ◽  
Interconnect Architectures ◽  
On Chip

On-chip Interconnect Trade-offs for Tera-scale Many-core Processors

2010 ◽  
pp. 263-296 ◽  
Author(s):  
Mani Azimi ◽  
Donglai Dai ◽  
Akhilesh Kumar ◽  
Aniruddha Vaidya
Keyword(s):  
Trade Offs ◽  
On Chip ◽  
Many Core
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