Design trade-offs for on-chip driving of high-speed high-performance ADCs in static BIST applications

2016 ◽  
Author(s):  
A. J. Gines ◽  
E. Peralias ◽  
G. Leger ◽  
A. Rueda ◽  
G. Renaud ◽  
...  
Keyword(s):  
High Speed ◽  
High Performance ◽  
Trade Offs ◽  
On Chip

scholarly journals Ultracompact and low-power-consumption silicon thermo-optic switch for high-speed data

Nanophotonics ◽  
2020 ◽  
Vol 10 (2) ◽  
pp. 937-945
Author(s):  
Ruihuan Zhang ◽  
Yu He ◽  
Yong Zhang ◽  
Shaohua An ◽  
Qingming Zhu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Pulse Amplitude ◽  
Telecommunication Networks ◽  
Low Power Consumption ◽  
Power Efficient ◽  
High Speed Data ◽  
On Chip

AbstractUltracompact and low-power-consumption optical switches are desired for high-performance telecommunication networks and data centers. Here, we demonstrate an on-chip power-efficient 2 × 2 thermo-optic switch unit by using a suspended photonic crystal nanobeam structure. A submilliwatt switching power of 0.15 mW is obtained with a tuning efficiency of 7.71 nm/mW in a compact footprint of 60 μm × 16 μm. The bandwidth of the switch is properly designed for a four-level pulse amplitude modulation signal with a 124 Gb/s raw data rate. To the best of our knowledge, the proposed switch is the most power-efficient resonator-based thermo-optic switch unit with the highest tuning efficiency and data ever reported.

CMOS INTEGRATED CIRCUIT CONTROLLERS FOR SWITCHING POWER CONVERTERS

2004 ◽  
Vol 13 (04) ◽  
pp. 789-811
Author(s):  
EDUARD ALARCÓN ◽  
GERARD VILLAR ◽  
ALBERTO POVEDA
Keyword(s):  
Integrated Circuit ◽  
High Speed ◽  
High Performance ◽  
Power Converters ◽  
Correct Operation ◽  
Case Examples ◽  
Cmos Integrated Circuit ◽  
Switching Power ◽  
Switching Power Converters ◽  
On Chip

Two case examples of high-speed CMOS microelectronic implementations of high-performance controllers for switching power converters are presented. The design and implementation of a current-programmed controller and a general-purpose feedforward one-cycle controller are described. The integrated circuit controllers attain high-performance by means of using current-mode analog signal processing, hence allowing high switching frequencies that extend the operation margin compared to previous designs. Global layout-extracted transistor-level simulation results for 0.8 μm and 0.35 μm standard CMOS technologies confirm both the correct operation of the circuits in terms of bandwidth as well as their functionality for the control of switching power converters. The circuits may be used either as standalone IC controllers or as controller circuits that are technology-compatible with on-chip switching power converters and on-chip loads for future powered systems-on-chip.

Si-Ge heterojunction bipolar technology for high-speed integrated circuits

1996 ◽  
Vol 74 (S1) ◽  
pp. 159-166
Author(s):  
D. C. Ahlgren ◽  
S. J. Jeng ◽  
D. Nguyen-Ngoc ◽  
K. Stein ◽  
D. Sunderland ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
High Performance ◽  
Full Range ◽  
Low Noise ◽  
Low Noise Amplifiers ◽  
Voltage Controlled Oscillators ◽  
Sige Hbt ◽  
Trade Offs ◽  
Scale Integration

This review discusses the fundamentals of SiGe epitaxial base heterojunction bipolar transistor (HBT) technology that have been developed for use in analog and mixed-signal applications in the 1–20 GHz range. The basic principles of operation of the graded base SiGe HBT are reviewed. These principles are then used to explore the design optimization for analog applications. Device results are presented that illustrate some important trade-offs in device design. A discussion of the use of UHV/CVD for the deposition of the epitaxial base profile is followed by an overview of the integrated process. This process, which has been installed on 200 mm wafers in IBM's Advanced Semiconductor Technology Center in Hopewell Junction, N.Y., also includes a full range of support devices. The process has demonstrated SiGe HBT performance, reliability, and yield in a CMOS fabrication with the addition of only one tool for UHV/CVD deposition of the epi-base and, with minimal additional process steps, can be used to fabricate full BiCMOS designs. This paper concludes with a discussion of high-performance circuits fabricated to date, including ECL ring'oscillators, power amplifiers, low-noise amplifiers, voltage-controlled oscillators, and finally a 12-bit DAC that features nearly 3000 SiGe HBT devices demonstrating medium-scale integration.

scholarly journals A New Router Architecture for High-Performance Intrachip Networks

2008 ◽  
Vol 3 (1) ◽  
pp. 23-31
Author(s):  
Everton Carara ◽  
Ney Calazans ◽  
Fernando Moraes
Keyword(s):  
High Performance ◽  
Packet Switching ◽  
Circuit Switching ◽  
Transmission Method ◽  
Communication Architecture ◽  
Virtual Channels ◽  
Trade Offs ◽  
Communication Architectures ◽  
Session Layer ◽  
On Chip

For almost a decade now, Network on Chip (NoC) concepts have evolved to provide an interesting alternative to more traditional intrachip communication architectures (e.g. shared busses) for the design of complex Systems on Chip (SoCs). A considerable number of NoC proposals are available, focusing on different sets of optimization aspects, related to specific classes of applications. Each such application employs a NoC as part of its underlying implementation infrastructure. Many of the mentioned optimization aspects target results such as Quality of Service (QoS) achievement and/or power consumption reduction. On the other hand, the use of NoCs brings about the solution of new design problems, such to the choice of synchronization method to employ between NoC routers and application modules mapping. Although the availability of NoC structures is already rather ample, some design choices are at base of many, if not most, NoC proposals. These include the use of wormhole packet switching and virtual channels. This work pledges against this practice. It discusses trade-offs of using circuit or packet switching, arguing in favor the use of the former with fixed size packets (cells). Quantitative data supports the argumentation. Also, the work proposes and justifies replacing the use of virtual channels by replicated channels, based on the abundance of wires in current and expected deep sub-micron technologies. Finally, the work proposes a transmission method coupling the use of session layer structures to circuit switching to better support application implementation. The main reported result is the availability of a router with reduced latency and area, a communication architecture adapted for high-performance applications.

scholarly journals Ultra-high speed reconfigurable microwave and radio frequency photonic intensity differentiators using Kerr frequency optical microcombs

2021 ◽  
Author(s):  
David Moss
Keyword(s):  
Radio Frequency ◽  
High Speed ◽  
High Performance ◽  
Third Order ◽  
Transversal Filter ◽  
Multi Wavelength ◽  
Gaussian Input ◽  
On Chip ◽  
The Cost ◽  
Good Agreement

Abstract We propose and experimentally demonstrate a microwave photonic intensity differentiator based on a Kerr optical comb generated by a compact integrated micro-ring resonator (MRR). The on-chip Kerr optical comb, containing a large number of comb lines, serves as a high-performance multi-wavelength source for the transversal filter, which will greatly reduce the cost, size, and complexity of the system. Moreover, owing to the compactness of the integrated MRR, up to 200-GHz frequency spacing of the Kerr optical comb can be achieved, enabling a potential operation bandwidth of over 100 GHz. By programming and shaping individual comb lines according to the calculated tap weights, a reconfigurable intensity differentiator with variable differentiation orders can be realized. The operation principle is theoretically analyzed, and experimental demonstrations of first-order, second-order, and third-order differentiation functions based on the principle are presented. The radio frequency (RF) amplitude and phase responses of multi-order intensity differentiations are characterized, and system demonstrations of real-time differentiations for Gaussian input signal are also performed. The experimental results show good agreement with theory, confirming the effectiveness of our approach.

Design and implementation of system-on-chip for peripheral component interconnect express encryption card based on multiple algorithms

Circuit World ◽  
2020 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Chen Kuilin ◽  
Feng Xi ◽  
Fu Yingchun ◽  
Liu Liang ◽  
Feng Wennan ◽  
...  
Keyword(s):  
Parallel Processing ◽  
High Speed ◽  
High Performance ◽  
Low Cost ◽  
Data Encryption ◽  
System On Chip ◽  
Content Type ◽  
Data Encryption Standard ◽  
Peripheral Component Interconnect ◽  
On Chip

Purpose The data protection is always a vital problem in the network era. High-speed cryptographic chip is an important part to ensure data security in information interaction. This paper aims to provide a new peripheral component interconnect express (PCIe) encryption card solution with high performance, high integration and low cost. Design/methodology/approach This work proposes a System on Chip architecture scheme of high-speed cryptographic chip for PCIe encryption card. It integrated CPU, direct memory access, the national and international cipher algorithm (data encryption standard/3 data encryption standard, Rivest–Shamir–Adleman, HASH, SM1, SM2, SM3, SM4, SM7), PCIe and other communication interfaces with advanced extensible interface-advanced high-performance bus three-level bus architecture. Findings This paper presents a high-speed cryptographic chip that integrates several high-speed parallel processing algorithm units. The test results of post-silicon sample shows that the high-speed cryptographic chip can achieve Gbps-level speed. That means only one single chip can fully meet the requirements of cryptographic operation performance for most cryptographic applications. Practical implications The typical application in this work is PCIe encryption card. Besides server’s applications, it can also be applied in terminal products such as high-definition video encryption, security gateway, secure routing, cloud terminal devices and industrial real-time monitoring system, which require high performance on data encryption. Social implications It can be well applied on many other fields such as power, banking, insurance, transportation and e-commerce. Originality/value Compared with the current strategy of high-speed encryption card, which mostly uses hardware field-programmable gate arrays or several low-speed algorithm chips through parallel processing in one printed circuit board, this work has provided a new PCIe encryption card solution with high performance, high integration and low cost only in one chip.

scholarly journals Dynamic Task Distribution Model for On-Chip Reconfigurable High Speed Computing System

2015 ◽  
Vol 2015 ◽  
pp. 1-12
Author(s):  
Mahendra Vucha ◽  
Arvind Rajawat
Keyword(s):  
High Speed ◽  
High Performance ◽  
Real Life ◽  
Computing System ◽  
Distribution Model ◽  
Design Parameters ◽  
Dynamic Task ◽  
Task Distribution ◽  
Field Programmable ◽  
On Chip

Modern embedded systems are being modeled as Reconfigurable High Speed Computing System (RHSCS) where Reconfigurable Hardware, that is, Field Programmable Gate Array (FPGA), and softcore processors configured on FPGA act as computing elements. As system complexity increases, efficient task distribution methodologies are essential to obtain high performance. A dynamic task distribution methodology based on Minimum Laxity First (MLF) policy (DTD-MLF) distributes the tasks of an application dynamically onto RHSCS and utilizes available RHSCS resources effectively. The DTD-MLF methodology takes the advantage of runtime design parameters of an application represented as DAG and considers the attributes of tasks in DAG and computing resources to distribute the tasks of an application onto RHSCS. In this paper, we have described the DTD-MLF model and verified its effectiveness by distributing some of real life benchmark applications onto RHSCS configured on Virtex-5 FPGA device. Some benchmark applications are represented as DAG and are distributed to the resources of RHSCS based on DTD-MLF model. The performance of the MLF based dynamic task distribution methodology is compared with static task distribution methodology. The comparison shows that the dynamic task distribution model with MLF criteria outperforms the static task distribution techniques in terms of schedule length and effective utilization of available RHSCS resources.

Linearity test of high-speed high-performance ADCs using a self-testable on-chip generator

2016 ◽  
Author(s):  
A. J. Gines ◽  
E. Peralias ◽  
G. Leger ◽  
A. Rueda ◽  
G. Renaud ◽  
...  
Keyword(s):  
High Speed ◽  
High Performance ◽  
On Chip ◽  
Linearity Test

scholarly journals Low latency Path Aware XY-X Routing Algorithm for NoC Architectures

2018 ◽  
Vol 7 (2.7) ◽  
pp. 763
Author(s):  
Venkateswara Rao Musala ◽  
T V Rama Krishna
Keyword(s):  
High Performance ◽  
Interconnection Network ◽  
Routing Algorithm ◽  
Adaptive Routing ◽  
Destination Node ◽  
Specific Information ◽  
Traffic Patterns ◽  
Traffic Conditions ◽  
Trade Offs ◽  
On Chip

Route specific information with the SoC needs a great deal of wiring, which increases the Resistance & Capacitance (RC) component of the system. Network on Chip (NoC) is utilized as the interface to address the problems in SoC, On-chip interconnection network in NoC has gained more consideration over steadfast wiring and buses, like lower latency, scalability and high performance. Present routing algorithms in NoC is suffered from load balancing at incarnation networks under non-uniform traffic conditions, causes increase the NoC trade-offs (latency and throughput). Adaptive routing is a technique to progress the load balance, but previous adaptive routing techniques used uniform traffic patterns to form the routing decisions. This paper proposes a new approach at non- uniform traffic patterns in channel state and path specific, Path Aware Routing (PAR XY-X) uses a timeout piggybacking for acknowledgement and load shedding to avoid congestion which choose optimistic path calculation unit to connect the destination node without glue logic decisions in routing. PAR XY-X outperforms the Normal XY routing by 20% and 33% with respect to Avg.latency and throughput.

Thermometer to Gray Encoders

2015 ◽  
pp. 323-335
Author(s):  
Yogendra Gupta ◽  
Sandeep Saini
Keyword(s):  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Gray Code ◽  
Direct Conversion ◽  
Flash Adc ◽  
Analog To Digital ◽  
Modulation Techniques ◽  
On Chip ◽  
Minimal Area

Analog to Digital Converter (ADC) is a key functional block in the design of mixed signal, system on chip, and signal processing applications. An optimized method for the direct conversion of analog signal to Gray code representation is presented. This eliminates the need for binary-to-Gray code conversion in many digital modulation techniques like M-PSK and M-QAM, which uses Gray coding representation to represent the symbols that are modulated. The authors design a low-power and high-speed Thermometer to Gray encoder for Flash ADC, as encoders have been widely utilized in high-performance critical applications which persistently impose special design constraints in terms of high-frequency, low power consumption, and minimal area. In this chapter, they propose a new circuit that converts the Thermometer code to Gray code and also yields minimized power.

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