Parallel turbo-sum-product decoder architecture for quasi-cyclic LDPC codes

2006 ◽  
Author(s):  
Yongmei Dai ◽  
Zhiyuan Yan ◽  
Ning Chen
Keyword(s):  
Ldpc Codes ◽  
Decoder Architecture

Half-row modified two-extra-column trellis min-max decoder architecture for nonbinary LDPC codes

Integration ◽  
2019 ◽  
Vol 69 ◽  
pp. 234-241
Author(s):  
Huyen Pham Thi ◽  
Hanho Lee ◽  
Xuan Nghia Pham
Keyword(s):  
Ldpc Codes ◽  
Decoder Architecture ◽  
Nonbinary Ldpc Codes

An Efficient VLSI Architecture for Nonbinary LDPC Decoder with Adaptive Message Control

2015 ◽  
Vol 4 (1) ◽  
pp. 6
Author(s):  
Varatharajan Ramachandran
Keyword(s):  
Power Consumption ◽  
Vlsi Architecture ◽  
Ldpc Codes ◽  
Parity Check ◽  
Decoding Complexity ◽  
Ldpc Decoder ◽  
Message Length ◽  
Low Density Parity Check ◽  
Decoder Architecture ◽  
Memory Accesses

<p>A new decoder architecture for nonbinary low-density parity check (LDPC) codes is presented in this paper to reduce the hardware operational complexity and power consumption. Adaptive message control (AMC) is to achieve the low decoding complexity,  that dynamically trims the message length of belief information to reduce the amount of memory accesses and arithmetic operations. A new horizontal nonbinary LDPC decoder architecture is developed to implement AMC. Key components in the architecture have been designed with the consideration of variable message lengths to leverage the benefit of the proposed AMC. Simulation results demonstrate that the proposed nonbinary LDPC decoder architecture can significantly reduce hardware operations and power consumption as compared with existing work with negligible performance degradation.</p>

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