An Efficient VLSI Architecture for Nonbinary LDPC Decoder with Adaptive Message Control

2015 ◽  
Vol 4 (1) ◽  
pp. 6
Author(s):  
Varatharajan Ramachandran
Keyword(s):  
Power Consumption ◽  
Vlsi Architecture ◽  
Ldpc Codes ◽  
Parity Check ◽  
Decoding Complexity ◽  
Ldpc Decoder ◽  
Message Length ◽  
Low Density Parity Check ◽  
Decoder Architecture ◽  
Memory Accesses

<p>A new decoder architecture for nonbinary low-density parity check (LDPC) codes is presented in this paper to reduce the hardware operational complexity and power consumption. Adaptive message control (AMC) is to achieve the low decoding complexity,  that dynamically trims the message length of belief information to reduce the amount of memory accesses and arithmetic operations. A new horizontal nonbinary LDPC decoder architecture is developed to implement AMC. Key components in the architecture have been designed with the consideration of variable message lengths to leverage the benefit of the proposed AMC. Simulation results demonstrate that the proposed nonbinary LDPC decoder architecture can significantly reduce hardware operations and power consumption as compared with existing work with negligible performance degradation.</p>

scholarly journals A New Reliability Ratio Weighted Bit Flipping Algorithm for Decoding LDPC Codes

2021 ◽  
Vol 2021 ◽  
pp. 1-11
Author(s):  
Chakir Aqil ◽  
Ismail Akharraz ◽  
Abdelaziz Ahaitouf
Keyword(s):  
Gaussian Noise ◽  
Additive White Gaussian Noise ◽  
Ldpc Codes ◽  
Low Density ◽  
Parity Check ◽  
Coding Gain ◽  
Decoding Complexity ◽  
Low Density Parity Check ◽  
Awgn Channel ◽  
Infinite Loop

In this study, we propose a “New Reliability Ratio Weighted Bit Flipping” (NRRWBF) algorithm for Low-Density Parity-Check (LDPC) codes. This algorithm improves the “Reliability Ratio Weighted Bit Flipping” (RRWBF) algorithm by modifying the reliability ratio. It surpasses the RRWBF in performance, reaching a 0.6 dB coding gain at a Binary Error Rate (BER) of 10−4 over the Additive White Gaussian Noise (AWGN) channel, and presents a significant reduction in the decoding complexity. Furthermore, we improved NRRWBF using the sum of the syndromes as a criterion to avoid the infinite loop. This will enable the decoder to attain a more efficient and effective decoding performance.

FPGA Implementation of a Novel Multi-Rate QC-LDPC Encoder for DTMB Standard

2013 ◽  
Vol 397-400 ◽  
pp. 2024-2027
Author(s):  
Fei Wang ◽  
Peng Zhang ◽  
Chang Yin Liu
Keyword(s):  
Power Consumption ◽  
Ldpc Codes ◽  
Fpga Implementation ◽  
Type I ◽  
Low Density ◽  
Parity Check ◽  
Encoding Scheme ◽  
Low Density Parity Check ◽  
Memory Resource ◽  
Simulation Results

A serial-input serial-output encoder based on pipelined type I rotate-left-accumulator (RLA) circuit is presented for multi-rate Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) codes of Digital Terrestrial Multimedia Broadcasting (DTMB) standard. This encoding scheme can reduce the power consumption and save memory resource. FPGA implementation and simulation results show that the design meets the requirement of DTMB standard and simplifies the structure of the memory.

scholarly journals LDPC Decoder of High Speed Multi-Rate DVB-S2 Based on FPGA

2019 ◽  
Vol 37 (2) ◽  
pp. 299-307 ◽  
Author(s):  
TianJiao Xie ◽  
Bo Li ◽  
Mao Yang ◽  
Zhongjiang Yan
Keyword(s):  
High Speed ◽  
State Of The Art ◽  
Ldpc Codes ◽  
The State ◽  
Elementary Transformation ◽  
Parity Check ◽  
Ldpc Decoder ◽  
Art Works ◽  
Decoder Architecture ◽  
Lower Triangular

A multi-rate LDPC decoder architecture for DVB-S2 codes based on FPGA is proposed. Through elementary transformation on the parity check matrices of DVB-S2 LDPC codes, a new matrix whose left is a QC sub-matrix and right is Transformation of Staircase lower triangular (TST) sub-matrix is obtained. The QC and TST are designed separately, therefore the successful experience of the most popular Quasi-Cyclic (QC) LDPC decoder architecture can be drawn on. While for TST sub-matrix, the variable nodes updating only need to be considered and the check nodes updating is realized compatibility with QC sub-matrix. Based on the proposed architectures, a multi-rate LDPC decoder implemented on Xilinx XC7VX485T FPGA can achieve the maximum decoding throughput of 2.5 Gbit/s at the 20 iterations when the operating frequency is 250 MHz, which demonstrates the highest throughput compared with the state-of-the-art works.

scholarly journals Conception of a new LDPC decoder with hardware implementation on FPGA card

2014 ◽  
Vol 3 (4) ◽  
pp. 451
Author(s):  
Anas El habti El idrissi ◽  
Rachid El Gouri ◽  
Hlou Laamari
Keyword(s):  
Error Detection ◽  
Matrix Equation ◽  
Coding Theory ◽  
Ldpc Codes ◽  
Low Density ◽  
Parity Check ◽  
Fast Encoding ◽  
Ldpc Decoder ◽  
Low Density Parity Check ◽  
Simplified Algorithm

Low Density Parity-Check codes are one of the hottest topics in coding theory nowadays. Equipped with very fast encoding and decoding algorithms, LDPC codes are very attractive both theoretically and practically. In this paper, A simplified algorithm for decoding Low-Density Parity-Check (LDPC) codes is proposed with a view to reduce the implementation complexity, this algorithm is based on a simple matrix equation which must be resolved in order to calculate all possible solutions of this equation, and then a simple circuit will be used to determine the errors produced during the transmission channel. First, we developed the design of the proposed algorithm second, we generated and simulated the hardware description language source code using Quartus software tools and finally we implemented the new algorithm of LDPC codes on FPGA card. Keywords: Bit-Flipping Algorithm, Error Detection, FPGA Card, LDPC Decoder, Matrix Equation.

Rate and Performance Enhancement of LDPC Codes Using Collection of Punctured Codes Decoding (CPCD)

2021 ◽  
Vol 11 ◽  
Author(s):  
Rana A. Hassan ◽  
John P. Fonseka
Keyword(s):  
Communication Systems ◽  
Ldpc Codes ◽  
Superior Performance ◽  
Low Density ◽  
Parity Check ◽  
Decoding Complexity ◽  
Low Density Parity Check ◽  
Punctured Codes ◽  
Punctured Code ◽  
Decoding Delay

Background: Low-density parity-check (LDPC) codes have received significant interest in a variety of communication systems due to their superior performance and reasonable decoding complexity. Methods: A novel collection of punctured codes decoding (CPCD) technique that considers a code as a collection of its punctured codes is proposed. Two forms of CPCD, serial CPCD that decodes each punctured code serially and parallel CPCD that decodes each punctured code in parallel, are discussed. Results: It is demonstrated that both serial and parallel CPCD have about the same decoding complexity compared with standard sum product algorithm (SPA) decoding. It is also demonstrated that while serial CPCD has about the same decoding delay compared with standard SPA decoding, parallel CPCD can decrease the decoding delay, however, at the expense of processing power. Conclusion: Numerical results demonstrate that CPCD can significantly improve the performance, or significantly increase the code rate of low-density parity-check (LDPC) codes.

scholarly journals Constructing LDPC Codes with Any Desired Girth

Sensors ◽  
2021 ◽  
Vol 21 (6) ◽  
pp. 2012
Author(s):  
Chaohui Gao ◽  
Sen Liu ◽  
Dong Jiang ◽  
Lijun Chen
Keyword(s):  
Wireless Sensor Networks ◽  
Sensor Networks ◽  
Power Consumption ◽  
Experimental Evidence ◽  
Ldpc Codes ◽  
Wireless Sensor ◽  
Low Density ◽  
Parity Check ◽  
Optimal Input ◽  
Low Density Parity Check

In wireless sensor networks, the reliability of communication can be greatly improved by applying low-density parity-check (LDPC) codes. Algorithms based on progressive-edge-growth (PEG) pattern and quasi-cyclic (QC) pattern are the mainstream approaches to constructing LDPC codes with good performance. However, these algorithms are not guaranteed to remove all short cycles to achieve the desired girth, and their excellent inputs are difficult to obtain. Herein, we propose an algorithm, which must be able to construct LDPC codes with the girth desired. In addition, the optimal input to the proposed algorithm is easy to find. Theoretical and experimental evidence of this study shows that the LDPC codes we construct have better decoding performance and less power consumption than the PEG-based and QC-based codes.

scholarly journals Reduced-complexity offset min-sum check node unit for layered 5G LDPC decoder

2021 ◽  
Vol 13 (1) ◽  
pp. 7-12
Author(s):  
Vladimir Petrović ◽  
Mezeni El
Keyword(s):  
Parity Check ◽  
Ldpc Decoder ◽  
Low Density Parity Check ◽  
Novel Approach ◽  
New Radio ◽  
Variable Weight ◽  
Decoder Architecture ◽  
Check Node ◽  
Higher Weights ◽  
Reduced Complexity

This paper presents a novel approach for the reduced-complexity Min-Sum (MS) decoding of low density parity check (LDPC) codes in the partially parallel layered decoder architecture, which contains a large number of serial check node processors. Reduced complexity is obtained by using the variant of the single-minimum Offset Min-Sum (smOMS) algorithm that approximates a second minimum with the addition of the variable weight parameter to the minimum value. Although the reduced-complexity MS algorithms primarily reduce hardware resources in fully parallel implementations, the results showed that a considerable reduction can be obtained if serial check node processors are used. The paper also proposes a better subminimum estimation for irregular codes from 5G new radio (5G NR). The method uses smaller subminimum estimation weights in check nodes with a higher degree and higher weights in check nodes with a smaller degree, which leads to the significant improvement in the SNR performance. Additionally, it is shown that SNR performance can be further improved by applying offset before minimum calculation, which differs from conventional Min-Sum approaches.

scholarly journals A Low-Complexity Euclidean Orthogonal LDPC Architecture for Low Power Applications

2015 ◽  
Vol 2015 ◽  
pp. 1-8
Author(s):  
M. Revathy ◽  
R. Saravanan
Keyword(s):  
Low Power ◽  
Low Complexity ◽  
Fourth Generation ◽  
Low Density ◽  
Parity Check ◽  
Ldpc Decoder ◽  
Low Density Parity Check ◽  
Variable Node ◽  
High Efficient ◽  
Decoder Architecture

Low-density parity-check (LDPC) codes have been implemented in latest digital video broadcasting, broadband wireless access (WiMax), and fourth generation of wireless standards. In this paper, we have proposed a high efficient low-density parity-check code (LDPC) decoder architecture for low power applications. This study also considers the design and analysis of check node and variable node units and Euclidean orthogonal generator in LDPC decoder architecture. The Euclidean orthogonal generator is used to reduce the error rate of the proposed LDPC architecture, which can be incorporated between check and variable node architecture. This proposed decoder design is synthesized on Xilinx 9.2i platform and simulated using Modelsim, which is targeted to 45 nm devices. Synthesis report proves that the proposed architecture greatly reduces the power consumption and hardware utilizations on comparing with different conventional architectures.

scholarly journals Low-complexity decoding of LDPC codes using reduced-set WBF-based algorithms

2020 ◽  
Vol 2020 (1) ◽  
Author(s):  
Sadjad Haddadi ◽  
Mahmoud Farhang ◽  
Mostafa Derakhtian
Keyword(s):  
Computational Complexity ◽  
Error Rate ◽  
Ldpc Codes ◽  
Low Complexity ◽  
Low Density ◽  
Parity Check ◽  
Decoding Complexity ◽  
Iterative Decoders ◽  
Low Density Parity Check ◽  
The Difference

Abstract We propose a method to substantially reduce the computational complexity of iterative decoders of low-density parity-check (LDPC) codes which are based on the weighted bit-flipping (WBF) algorithm. In this method, the WBF-based decoders are modified so that the flipping function is calculated only over a reduced set of variable nodes. An explicit expression for the achieved complexity gain is provided and it is shown that for a code of block length N, the decoding complexity is reduced from O(N2) to O(N). Moreover, we derive an upper bound for the difference in the frame error rate of the reduced-set decoders and the original WBF-based decoders, and it is shown that the error performances of the two decoders are essentially the same.

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