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Parametric fault simulation and test vector generation
Proceedings of the conference on Design, automation and test in Europe - DATE '00
◽
10.1145/343647.343883
◽
2000
◽
Cited By ~ 7
Author(s):
Khaled Saab
◽
Naim Ben-Hamida
◽
Bozena Kaminska
Keyword(s):
Fault Simulation
◽
Test Vector
◽
Vector Generation
◽
Parametric Fault
◽
Test Vector Generation
Download Full-text
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Cited By
References
Parametric fault simulation and test vector generation
Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537)
◽
10.1109/date.2000.840855
◽
2002
◽
Cited By ~ 21
Author(s):
K. Saab
◽
N. Ben-Hamida
◽
B. Kaminska
Keyword(s):
Fault Simulation
◽
Test Vector
◽
Vector Generation
◽
Parametric Fault
◽
Test Vector Generation
Download Full-text
Ping-pong test: Compact test vector generation for reversible circuits
2012 IEEE 30th VLSI Test Symposium (VTS)
◽
10.1109/vts.2012.6231097
◽
2012
◽
Cited By ~ 10
Author(s):
Masoud Zamani
◽
Mehdi B. Tahoori
◽
Krishnendu Chakrabarty
Keyword(s):
Test Vector
◽
Reversible Circuits
◽
Vector Generation
◽
Ping Pong
◽
Test Vector Generation
◽
Compact Test
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On-Line Test Vector Generation from Temporal Regular Expressions
2006 6th International Workshop on System on Chip for Real Time Applications
◽
10.1109/iwsoc.2006.348223
◽
2006
◽
Author(s):
Yann Oddos
◽
Katell Morin-Allory
◽
Dominique Borrione
Keyword(s):
Regular Expressions
◽
Test Vector
◽
Vector Generation
◽
On Line
◽
Line Test
◽
Test Vector Generation
Download Full-text
Automation of Translating Unit-Level Verification Scenarios for Test Vector Generation of SoC
Intelligent Sustainable Systems - Lecture Notes in Networks and Systems
◽
10.1007/978-981-16-6309-3_50
◽
2022
◽
pp. 527-536
Author(s):
Rahul Anilkumar
◽
B. K. S. V. L. Varaprasad
◽
K. Padmapriya
Keyword(s):
Test Vector
◽
Unit Level
◽
Vector Generation
◽
Test Vector Generation
Download Full-text
Observability-based coverage-directed path search using PBO for automatic test vector generation
2009 17th IFIP International Conference on Very Large Scale Integration (VLSI-SoC)
◽
10.1109/vlsisoc.2009.6041346
◽
2009
◽
Cited By ~ 1
Author(s):
Jose C. Costa
◽
Jose C. Monteiro
Keyword(s):
Test Vector
◽
Directed Path
◽
Automatic Test
◽
Vector Generation
◽
Path Search
◽
Test Vector Generation
Download Full-text
Behavioral-level test vector generation for system-on-chip designs
Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786)
◽
10.1109/hldvt.2000.889554
◽
2002
◽
Cited By ~ 11
Author(s):
M. Lajolo
◽
M. Rebaudengo
◽
M.S. Reorda
◽
M. Violante
◽
L. Lavagno
Keyword(s):
System On Chip
◽
Test Vector
◽
Behavioral Level
◽
Vector Generation
◽
On Chip
◽
Test Vector Generation
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New Metric Based Algorithm for Test Vector Generation in VLSI Testing
Defence Science Journal
◽
10.14429/dsj.45.4132
◽
1995
◽
Vol 45
(3)
◽
pp. 255-265
Author(s):
M.V. Atre
◽
V. Latha
Keyword(s):
Test Vector
◽
Vlsi Testing
◽
Vector Generation
◽
Test Vector Generation
Download Full-text
An assembler approach to the automation of test vector generation
10.1109/asic.1990.186180
◽
2002
◽
Author(s):
K. Perrey
◽
M. Manley
Keyword(s):
Test Vector
◽
Vector Generation
◽
Test Vector Generation
Download Full-text
Test vector generation and classification using FSM traversals
2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)
◽
10.1109/iscas.2004.1329524
◽
2004
◽
Author(s):
R. Marczynski
◽
M.A. Thornton
◽
S.A. Szygenda
Keyword(s):
Test Vector
◽
Vector Generation
◽
Test Vector Generation
Download Full-text
Test vector generation for charge sharing failures in dynamic logic
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
◽
10.1109/tcad.2002.804377
◽
2002
◽
Vol 21
(12)
◽
pp. 1502-1508
Author(s):
K. Heragu
◽
M. Sharma
◽
R. Kundu
◽
R.D. Blanton
Keyword(s):
Dynamic Logic
◽
Test Vector
◽
Charge Sharing
◽
Vector Generation
◽
Test Vector Generation
Download Full-text
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