A Dynamic Huffman Coding Method for Reliable TLC NAND Flash Memory

2021 ◽  
Vol 26 (5) ◽  
pp. 1-25
Author(s):  
Chin-Hsien Wu ◽  
Hao-Wei Zhang ◽  
Chia-Wei Liu ◽  
Ta-Ching Yu ◽  
Chi-Yen Yang

With the progress of the manufacturing process, NAND flash memory has evolved from the single-level cell and multi-level cell into the triple-level cell (TLC). NAND flash memory has physical problems such as the characteristic of erase-before-write and the limitation of program/erase cycles. Moreover, TLC NAND flash memory has low reliability and short lifetime. Thus, we propose a dynamic Huffman coding method that can apply to the write operations of NAND flash memory. The proposed method exploits observations from a Huffman tree and machine learning from data patterns to dynamically select a suitable Huffman coding. According to the experimental results, the proposed method can improve the reliability of TLC NAND flash memory and also consider the compression performance for those applications that require the Huffman coding.

2007 ◽  
Vol 42 (1) ◽  
pp. 219-232 ◽  
Author(s):  
Ken Takeuchi ◽  
Yasushi Kameda ◽  
Susumu Fujimura ◽  
Hiroyuki Otake ◽  
Koji Hosono ◽  
...  

2013 ◽  
Vol 60 (6) ◽  
pp. 4451-4456 ◽  
Author(s):  
J. David Ingalls ◽  
Matthew J. Gadlage ◽  
Adam R. Duncan ◽  
Matthew J. Kay ◽  
Patrick L. Cole ◽  
...  

2021 ◽  
Author(s):  
Jisuk Kim ◽  
Earl Kim ◽  
Daehyeon Lee ◽  
Taeheon Lee ◽  
Daesik Ham ◽  
...  

Abstract In the NAND flash manufacturing process, thousands of internal electronic fuses (eFuse) should be tuned in order to optimize performance and validity. In this paper, we propose a machine learning-based optimization technique that can automatically tune the individual eFuse value based on a deep learning and genetic algorithm. Using state-of-the-art triple-level cell (TLC) V-NAND flash wafers, we trained our model and validated its effectiveness. The experimental results show that our technique can automatically optimize NAND flash memory, thus reducing total turnaround time (TAT) by 70 % compared with the manual-based process.


2020 ◽  
Vol 20 (7) ◽  
pp. 4138-4142
Author(s):  
Sung-Tae Lee ◽  
Suhwan Lim ◽  
Nagyong Choi ◽  
Jong-Ho Bae ◽  
Dongseok Kwon ◽  
...  

NAND flash memory which is mature technology has great advantage in high density and great storage capacity per chip because cells are connected in series between a bit-line and a source-line. Therefore, NAND flash cell can be used as a synaptic device which is very useful for a high-density synaptic array. In this paper, the effect of the word-line bias on the linearity of multi-level conductance steps of the NAND flash cell is investigated. A 3-layer perceptron network (784×200×10) is trained by a suitable weight update method for NAND flash memory using MNIST data set. The linearity of multi-level conductance steps is improved as the word line bias increases from Vth −0.5 to Vth +1 at a fixed bit-line bias of 0.2 V. As a result, the learning accuracy is improved as the word-line bias increases from Vth −0.5 to Vth+1.


Author(s):  
Wandong Kim ◽  
Joo Yun Seo ◽  
Yoon Kim ◽  
Se Hwan Park ◽  
Sang Ho Lee ◽  
...  

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