Machine learning for design and optimization challenges in multi/many-core network-on-chip

2021 ◽  
Author(s):  
Md Farhadur Reza
Keyword(s):  
Machine Learning ◽  
Network On Chip ◽  
Core Network ◽  
Design And Optimization ◽  
On Chip ◽  
Many Core

A Reconfigurable On-die Traffic Generator in 45nm CMOS for a 48 iA-32 Core Network-on-Chip

2012 ◽  
Author(s):  
Praveen Salihundam ◽  
Mohammed Asadullah Khan ◽  
Shailendra Jain ◽  
Yatin Hoskote ◽  
Satish Yada ◽  
...  
Keyword(s):  
Network On Chip ◽  
Core Network ◽  
Traffic Generator ◽  
On Chip

FoToNoC: A Folded Torus-Like Network-on-Chip Based Many-Core Systems-on-Chip in the Dark Silicon Era

2017 ◽  
Vol 28 (7) ◽  
pp. 1905-1918 ◽  
Author(s):  
Lei Yang ◽  
Weichen Liu ◽  
Weiwen Jiang ◽  
Mengquan Li ◽  
Peng Chen ◽  
...  
Keyword(s):  
Network On Chip ◽  
Dark Silicon ◽  
Systems On Chip ◽  
On Chip ◽  
Many Core

A Novel Hybrid Cache Coherence with Global Snooping for Many-core Architectures

2022 ◽  
Vol 27 (1) ◽  
pp. 1-31
Author(s):  
Sri Harsha Gade ◽  
Sujay Deb
Keyword(s):  
Lower Energy ◽  
Cache Coherence ◽  
Network On Chip ◽  
Highly Efficient ◽  
Wireless Links ◽  
Coherence Protocols ◽  
High Area ◽  
On Chip ◽  
Many Core ◽  
Clustered Network

Cache coherence ensures correctness of cached data in multi-core processors. Traditional implementations of existing protocols make them unscalable for many core architectures. While snoopy coherence requires unscalable ordered networks, directory coherence is weighed down by high area and energy overheads. In this work, we propose Wireless-enabled Share-aware Hybrid (WiSH) to provide scalable coherence in many core processors. WiSH implements a novel Snoopy over Directory protocol using on-chip wireless links and hierarchical, clustered Network-on-Chip to achieve low-overhead and highly efficient coherence. A local directory protocol maintains coherence within a cluster of cores, while coherence among such clusters is achieved through global snoopy protocol. The ordered network for global snooping is provided through low-latency and low-energy broadcast wireless links. The overheads are further reduced through share-aware cache segmentation to eliminate coherence for private blocks. Evaluations show that WiSH reduces traffic by and runtime by , while requiring smaller storage and lower energy as compared to existing hierarchical and hybrid coherence protocols. Owing to its modularity, WiSH provides highly efficient and scalable coherence for many core processors.

An Overview of Multi-Core Network-on-Chip System to Enable Task Parallelization Using Intelligent Adaptive Arbitration

2021 ◽  
pp. 15-38
Author(s):  
Mohammad Nishat Akhtar ◽  
Qummare Azam ◽  
Tarik Adnan Almohamad ◽  
Junita Mohamad-Saleh ◽  
Elmi Abu Bakar ◽  
...  
Keyword(s):  
Network On Chip ◽  
Core Network ◽  
On Chip
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