Effective Defect Control in TiN Metal Hard Mask Cu/Low-k Dual Damascene Process

ECS Transactions ◽

10.1149/05806.0143ecst ◽

2013 ◽

Vol 58 (6) ◽

pp. 143-150 ◽

Author(s):

A. Kabansky ◽

S. S. H. Tan ◽

E. A. Hudson ◽

G. Delgadino ◽

L. Gancs ◽

...

Keyword(s):

Hard Mask ◽

Dual Damascene ◽

Damascene Process ◽

Defect Control ◽

Tin Metal ◽

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Effective Defect Control in TiN Metal Hard Mask Cu/Low-k Dual Damascene Process

ECS Meeting Abstracts ◽

10.1149/ma2013-02/30/2112 ◽

2013 ◽

Keyword(s):

Hard Mask ◽

Dual Damascene ◽

Damascene Process ◽

Defect Control ◽

Tin Metal ◽

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Aqueous Based Single Wafer Cu/Low-k Cleaning Process Characterization and Integration into Dual Damascene Process Flow

Solid State Phenomena - Ultra Clean Processing of Silicon Surfaces VII ◽

10.4028/3-908451-06-x.353 ◽

2005 ◽

pp. 353-356

Author(s):

Jian She Tang ◽

Brian J. Brown ◽

Steven Verhaverbeke ◽

Han Wen Chen ◽

Jim Papanu ◽

...

Keyword(s):

Cleaning Process ◽

Process Flow ◽

Dual Damascene ◽

Damascene Process ◽

Process Characterization ◽

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Highly manufacturable Cu/low-k dual damascene process integration for 65nm technology node

Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729) ◽

10.1109/iitc.2004.1345683 ◽

2004 ◽

Author(s):

K.-W. Lee ◽

H.J. Shin ◽

J.W. Hwang ◽

S.W. Nam ◽

Y.J. Moon ◽

...

Keyword(s):

Process Integration ◽

Technology Node ◽

Dual Damascene ◽

Damascene Process ◽

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Misalignment-tolerated, Cu dual damascene interconnects with low-k SiOCH film by a novel via-first, multi-hard-mask process for sub-100nm-node, ASICs

IEEE International Electron Devices Meeting 2003 ◽

10.1109/iedm.2003.1269413 ◽

2004 ◽

Author(s):

H. Ohtake ◽

M. Tagami ◽

K. Arita ◽

Y. Hayashi

Keyword(s):

Hard Mask ◽

Dual Damascene ◽

Damascene Interconnects ◽

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A HSQ-based inorganic sacrificial via filler-assisted 90 nm-node Cu/low-k OSG dual damascene process integration

2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407) ◽

10.1109/vlsit.2003.1221119 ◽

2004 ◽

Author(s):

K.-W. Lee ◽

S.G. Lee ◽

W.J. Park ◽

B.J. Oh ◽

J.H. Kim ◽

...

Keyword(s):

Process Integration ◽

Dual Damascene ◽

Damascene Process ◽

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Dual-Damascene Cu/Low-k Interconnect Fabrication Scheme Using Dissoluble Hard Mask Material

Journal of The Electrochemical Society ◽

10.1149/1.2149297 ◽

2006 ◽

Vol 153 (2) ◽

pp. G160 ◽

Author(s):

Takeshi Furusawa ◽

Shuntaro Machida ◽

Daisuke Ryuzaki ◽

Kenji Sameshima ◽

Takeshi Ishida ◽

...

Keyword(s):

Hard Mask ◽

Dual Damascene ◽

Mask Material ◽

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Influence of visco-elasticity of low-k dielectrics on thermo-mechanical behavior of dual damascene process

Fifth International Conference onElectronic Packaging Technology Proceedings, 2003. ICEPT2003. ◽

10.1109/eptc.2003.1298742 ◽

2003 ◽

Author(s):

V. Gonda ◽

G.Q. Zhang ◽

J. den Toonder ◽

J. Beijer ◽

L.J. Ernst

Keyword(s):

Mechanical Behavior ◽

Dual Damascene ◽

Damascene Process ◽

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Degradation of the Barrier Integrity of Porous Low-k Dual Damascene Interconnects Using Dual Top Hard Mask Process Integration

Journal of the Korean Physical Society ◽

10.3938/jkps.54.1671 ◽

2009 ◽

Vol 54 (4) ◽

pp. 1671-1674

Author(s):

Sung Gyu Pyo ◽

Sang-Young Kim

Keyword(s):

Process Integration ◽

Barrier Integrity ◽

Hard Mask ◽

Dual Damascene ◽

Damascene Interconnects ◽

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A novel clustered hard mask technology for dual damascene multilevel interconnects with self-aligned via formation using an organic low k dielectric

1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325) ◽

10.1109/vlsit.1999.799330 ◽

2003 ◽

Author(s):

N. Aoi ◽

E. Tamaoka ◽

M. Yamanaka ◽

S. Hirao ◽

T. Ueda ◽

...

Keyword(s):

Hard Mask ◽

Dual Damascene ◽

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Dual hard mask process for low-k porous organosilica dielectric in copper dual damascene interconnect fabrication

10.1109/iitc.2001.930088 ◽

2001 ◽

Author(s):

M. Hiroi ◽

M. Tada ◽

H. Ohtake ◽

S. Saito ◽

T. Onodera ◽

...

Keyword(s):

Hard Mask ◽

Dual Damascene ◽

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