Cell Design Consideration Concerning Cell Failure Mechanism

2021 ◽  
Vol MA2021-02 (3) ◽  
pp. 421-421
Author(s):  
Jaesik Chung ◽  
Giovanni Flores ◽  
Kwang Jung
2020 ◽  
Author(s):  
Gracieli Posser ◽  
Ricardo Reis ◽  
Sachin S. Sapatnekar

Electromigration (EM) in on-chip metal interconnects is a critical reliability failure mechanism in nanometer-scale technologies. This work addresses the problem of EM on signal interconnects and on Vdd and Vss rails within a standard cell. An approach for modeling and efficient characterization of cell-internal EM is developed, incorporating Joule heating effects. We also present a graph-based algorithm that computes the currents when the pin position is moved avoiding a new characterization for each pin position and consequently reducing considerable the characterization time. We use the cell lifetime analysis to determine the lifetime of large benchmark circuits, and show that these circuit lifetimes can be improved up to 80.95% by avoiding the critical output, Vdd, and Vss pin positions of the cells, using minor layout modifications.


Author(s):  
J. R. Sellar ◽  
J. M. Cowley

Current interest in high voltage electron microscopy, especially in the scanning mode, has prompted the development of a method for determining the contrast and resolution of images of specimens in controlled-atmosphere stages or open to the air, hydrated biological specimens being a good example. Such a method would be of use in the prediction of microscope performance and in the subsequent optimization of environmental cell design for given circumstances of accelerating voltage, cell gas pressure and constitution, and desired resolution.Fig. 1 depicts the alfresco cell of a focussed scanning transmission microscope with a layer of gas L (and possibly a thin window W) between the objective O and specimen T. Using the principle of reciprocity, it may be considered optically equivalent to a conventional transmission electron microscope, if the beams were reversed. The layer of gas or solid material after the specimen in the STEM or before the specimen in TEM has no great effect on resolution or contrast and so is ignored here.


Author(s):  
Jin Young Kim ◽  
R. E. Hummel ◽  
R. T. DeHoff

Gold thin film metallizations in microelectronic circuits have a distinct advantage over those consisting of aluminum because they are less susceptible to electromigration. When electromigration is no longer the principal failure mechanism, other failure mechanisms caused by d.c. stressing might become important. In gold thin-film metallizations, grain boundary grooving is the principal failure mechanism.Previous studies have shown that grain boundary grooving in gold films can be prevented by an indium underlay between the substrate and gold. The beneficial effect of the In/Au composite film is mainly due to roughening of the surface of the gold films, redistribution of indium on the gold films and formation of In2O3 on the free surface and along the grain boundaries of the gold films during air annealing.


1983 ◽  
Vol 44 (C3) ◽  
pp. C3-1195-C3-1199
Author(s):  
H. Anzai ◽  
T. Moriya ◽  
K. Nozaki ◽  
T. Ukachi ◽  
G. Saito

2008 ◽  
Vol 11 (-1) ◽  
pp. 188-201 ◽  
Author(s):  
Piotr Bogacz ◽  
Jarosława Kaczmarek ◽  
Danuta Leśniewska

Author(s):  
William Ng ◽  
Kevin Weaver ◽  
Zachary Gemmill ◽  
Herve Deslandes ◽  
Rudolf Schlangen

Abstract This paper demonstrates the use of a real time lock-in thermography (LIT) system to non-destructively characterize thermal events prior to the failing of an integrated circuit (IC) device. A case study using a packaged IC mounted on printed circuit board (PCB) is presented. The result validated the failing model by observing the thermal signature on the package. Subsequent analysis from the backside of the IC identified a hot spot in internal circuitry sensitive to varying value of external discrete component (inductor) on PCB.


Author(s):  
Sarven Ipek ◽  
David Grosjean

Abstract The application of an individual failure analysis technique rarely provides the failure mechanism. More typically, the results of numerous techniques need to be combined and considered to locate and verify the correct failure mechanism. This paper describes a particular case in which different microscopy techniques (photon emission, laser signal injection, and current imaging) gave clues to the problem, which then needed to be combined with manual probing and a thorough understanding of the circuit to locate the defect. By combining probing of that circuit block with the mapping and emission results, the authors were able to understand the photon emission spots and the laser signal injection microscopy (LSIM) signatures to be effects of the defect. It also helped them narrow down the search for the defect so that LSIM on a small part of the circuit could lead to the actual defect.


Author(s):  
John Butchko ◽  
Bruce T. Gillette

Abstract Autoclave Stress failures were encountered at the 96 hour read during transistor reliability testing. A unique metal corrosion mechanism was found during the failure analysis, which was creating a contamination path to the drain source junction, resulting in high Idss and Igss leakage. The Al(Si) top metal was oxidizing along the grain boundaries at a faster rate than at the surface. There was subsurface blistering of the Al(Si), along with the grain boundary corrosion. This blistering was creating a contamination path from the package to the Si surface. Several variations in the metal stack were evaluated to better understand the cause of the failures and to provide a process solution. The prevention of intergranular metal corrosion and subsurface blistering during autoclave testing required a materials change from Al(Si) to Al(Si)(Cu). This change resulted in a reduced corrosion rate and consequently prevented Si contamination due to blistering. The process change resulted in a successful pass through the autoclave testing.


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