scholarly journals CMOS Image Sensor with On-Chip Image Compression: A Review and Performance Analysis

2010 ◽  
Vol 2010 ◽  
pp. 1-17 ◽  
Author(s):  
Milin Zhang ◽  
Amine Bermak
Keyword(s):  
Image Processing ◽  
Performance Analysis ◽  
Image Compression ◽  
High Performance ◽  
Cmos Technology ◽  
Image Sensor ◽  
Processing Unit ◽  
Cmos Image Sensors ◽  
Design Paradigm ◽  
On Chip

Demand for high-resolution, low-power sensing devices with integrated image processing capabilities, especially compression capability, is increasing. CMOS technology enables the integration of image sensing and image processing, making it possible to improve the overall system performance. This paper reviews the current state of the art in CMOS image sensors featuring on-chip image compression. Firstly, typical sensing systems consisting of separate image-capturing unit and image-compression processing unit are reviewed, followed by systems that integrate focal-plane compression. The paper also provides a thorough review of a new design paradigm, in which image compression is performed during the image-capture phase prior to storage, referred to as compressive acquisition. High-performance sensor systems reported in recent years are also introduced. Performance analysis and comparison of the reported designs using different design paradigm are presented at the end.

A High Performance Image Processing Unit for On-orbit Servicing

2006 ◽  
Author(s):  
Hiroshi Yamamoto ◽  
Yasufumi Nagai ◽  
Shinichi Kimura ◽  
Hiroshi Takahashi ◽  
Satoko Mizumoto ◽  
...  
Keyword(s):  
Image Processing ◽  
High Performance ◽  
Processing Unit

scholarly journals Toward a fully integrated automotive radar system-on-chip in 22 nm FD-SOI CMOS

2021 ◽  
pp. 1-9
Author(s):  
Philipp Ritter
Keyword(s):  
Millimeter Wave ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Digital Signal ◽  
Cmos Technology ◽  
Radar System ◽  
Circuit Board ◽  
Processing Unit ◽  
Automotive Radar ◽  
On Chip

Abstract Next-generation automotive radar sensors are increasingly becoming sensitive to cost and size, which will leverage monolithically integrated radar system-on-Chips (SoC). This article discusses the challenges and the opportunities of the integration of the millimeter-wave frontend along with the digital backend. A 76–81 GHz radar SoC is presented as an evaluation vehicle for an automotive, fully depleted silicon-over-insulator 22 nm CMOS technology. It features a digitally controlled oscillator, 2-millimeter-wave transmit channels and receive channels, an analog base-band with analog-to-digital conversion as well as a digital signal processing unit with on-chip memory. The radar SoC evaluation chip is packaged and flip-chip mounted to a high frequency printed circuit board for functional demonstration and performance evaluation.

Design of a Reconfigurable Coprocessor for Double Precision Floating Point Matrix Algorithms

2011 ◽  
Vol 58-60 ◽  
pp. 1037-1042
Author(s):  
Sheng Long Li ◽  
Zhao Lin Li ◽  
Qing Wei Zheng
Keyword(s):  
High Performance ◽  
Cmos Technology ◽  
General Purpose ◽  
Floating Point ◽  
Double Precision ◽  
Synthesis Time ◽  
Matrix Algorithms ◽  
Matrix Operations ◽  
On Chip ◽  
Software Execution

Double precision floating point matrix operations are wildly used in a variety of engineering and scientific computing applications. However, it’s inefficient to achieve these operations using software approaches on general purpose processors. In order to reduce the processing time and satisfy the real-time demand, a reconfigurable coprocessor for double precision floating point matrix algorithms is proposed in this paper. The coprocessor is embedded in a Multi-Processor System on Chip (MPSoC), cooperates with an ARM core and a DSP core for high-performance control and calculation. One algorithm in GPS applications is taken for example to illustrate the efficiency of the coprocessor proposed in this paper. The experiment result shows that the coprocessor can achieve speedup a factor of 50 for the quaternion algorithm of attitude solution in inertial navigation application compare with software execution time of a TI C6713 DSP. The coprocessor is implemented in SMIC 0.13μm CMOS technology, the synthesis time delay is 9.75ns, and the power consumption is 63.69 mW when it works at 100MHz.

A Wearable Supporting System for Visually Impaired People in Operating Capacitive Touchscreen

2011 ◽  
Vol 103 ◽  
pp. 687-694
Author(s):  
Akira Yamawaki ◽  
Serikawa Seiichi
Keyword(s):  
Image Processing ◽  
Visually Impaired ◽  
High Performance ◽  
Middle Finger ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Supporting System ◽  
Visually Impaired People ◽  
Impaired People ◽  
Natural Way

We propose a wearable supporting system with a CMOS image sensor for the visually impaired people in operating capacitive touchscreen. This system attaches the CMOS image sensor without a lens to the tip of the middle finger. The icons and buttons displayed on the touchscreen are replaced to the color barcodes. Touching the surface of the touchscreen with the CMOS image sensor directly, the color barcode is detected and decoded. The decoded results are returned to the user by some interaction like audio. Then, the user touches the button area around the color barcode by the forefinger to operate the target device. This system can provide very easy and natural way for operating the touchscreen to the visually impaired people who usually recognize the materials by the finger. Any mechanical modification of the target device is not needed. The modification can be made by changing its software program. Since the color barcode is sensed by the image sensor without any lens touching the surface of the touchscreen, each bar in the color barcode should be blurred. So, we　develop an easy and simple image processing to handle such problem. We design it as the hardware module to achieve the high performance and low-power wearable device. A prototype hardware using an FPGA shows the hardware size, the performance and the actual demonstration.

scholarly journals Computing Sorted Subsets for Data Processing in Communicating Software/Hardware Control Systems

2015 ◽  
Vol 11 (1) ◽  
pp. 126 ◽  
Author(s):  
Valery Sklyarov ◽  
Iouliia Skliarova ◽  
Artjom Rjabov ◽  
Alexander Sudnitson
Keyword(s):  
High Performance ◽  
Large Data ◽  
Computation Method ◽  
Data Sets ◽  
Processing Unit ◽  
Programmable Logic ◽  
Practical Applications ◽  
Sorting Networks ◽  
Hardware System ◽  
On Chip

Computing and filtering sorted subsets are frequently required in statistical data manipulation and control applications. The main objective is to extract subsets from large data sets in accordance with some criteria, for example, with the maximum and/or the minimum values in the entire set or within the predefined constraints. The paper suggests a new computation method enabling the indicated above problem to be solved in all programmable systems-on-chip from the Xilinx Zynq family that combine a dual-core Cortex-A9 processing unit and programmable logic linked by high-performance interfaces. The method involves highly parallel sorting networks and run-time filtering. The computations are done in communicating software, running in the processing unit, and hardware, implemented in the programmable logic. Practical applications of the proposed technique are also shown. The results of implementation and experiments clearly demonstrate significant speed-up of the developed software/hardware system comparing to alternative software implementations.

scholarly journals A CMOS voltage-mode image sensing system

2021 ◽  
Author(s):  
Jun Long Zhang
Keyword(s):  
Cmos Image Sensor ◽  
Cmos Technology ◽  
Image Sensor ◽  
Electrical Signal ◽  
Image Sensors ◽  
Analog To Digital ◽  
Light Sensing ◽  
Image Sensing ◽  
Cmos Image Sensors ◽  
Pixel Sensors

A CMOS image sensor consists of a light sensing region that converts photonic energy to an electrical signal and a peripheral circuitry that performs signal conditioning and post-processing. This project investgates the principle and design of CMOS active image sensors. The basic concepts and principle of CMOS image sensors are investigated. The advantages of CMOS image sensors over charge-coupled device (CCD) image sensors are presented. Both passive pixel sensors (PPS) and acive pixel sensors (APS) are examined in detail. The noise of CMOS image sensors is investigated and correlated double sampling (CDS) techniques are examined. The design of APS arrays, CDS circuits and 8-bit analog to-digital converters in TSMC-0.18μm 1.8V CMOS technology is presented. The simulation results and layout of the designed CMOS image sensor are presented.

On-chip polarizer on image sensor using advanced CMOS technology

2014 ◽  
Author(s):  
Kiyotaka Sasagawa ◽  
Norimitsu Wakama ◽  
Toshihiko Noda ◽  
Takashi Tokuda ◽  
Kiyomi Kakiuchi ◽  
...  
Keyword(s):  
Cmos Technology ◽  
Image Sensor ◽  
On Chip
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