scholarly journals Flash FPGA-Based Numerical Pulse-Width Modulator

2011 ◽  
Vol 2011 ◽  
pp. 1-6 ◽  
Author(s):  
Ricardo Arias ◽  
Hernán Mediote ◽  
Hernán Tacca
Keyword(s):  
Field Programmable Gate Array ◽  
Pulse Width ◽  
Hybrid Approach ◽  
Fpga Implementation ◽  
Modulation Technique ◽  
Ac Motors ◽  
Pulse Width Modulator ◽  
Three Phase ◽  
Field Programmable ◽  
Gate Array

A pulse-width modulator to drive three-phase AC motors is described. It performs a numerical modulation technique, also known as optimum or calculated modulation, but, in order to reduce hardware resources, a hybrid approach merging that calculated modulation with proportional modulation is proposed. The modulator is tested in a flash-based field programmable gate array (FPGA) implementation.

scholarly journals Novel Binary Signed-Digit Addition Algorithm for FPGA Implementation

2019 ◽  
Vol 29 (09) ◽  
pp. 2050136
Author(s):  
Yuuki Tanaka ◽  
Yuuki Suzuki ◽  
Shugang Wei
Keyword(s):  
Field Programmable Gate Array ◽  
High Speed ◽  
Number System ◽  
Logic Circuit ◽  
Fpga Implementation ◽  
Number Representation ◽  
Representation System ◽  
Representation Systems ◽  
Field Programmable ◽  
Gate Array

Signed-digit (SD) number representation systems have been studied for high-speed arithmetic. One important property of the SD number system is the possibility of performing addition without long carry chain. However, many numbers of logic elements are required when the number representation system and such an adder are realized on a logic circuit. In this study, we propose a new adder on the binary SD number system. The proposed adder uses more circuit area than the conventional SD adders when those adders are realized on ASIC. However, the proposed adder uses 20% less number of logic elements than the conventional SD adder when those adders are realized on a field-programmable gate array (FPGA) which is made up of 4-input 1-output LUT such as Intel Cyclone IV FPGA.

Performance Analysis of FPGA based Diode Clamped Multilevel Inverter Fed Induction Motor Drive using Phase Opposition Disposition Multicarrier Based Modulation Strategy

2017 ◽  
Vol 8 (4) ◽  
pp. 1512
Author(s):  
Nunsavath Susheela ◽  
Satish Kumar
Keyword(s):  
Induction Motor ◽  
Pulse Width ◽  
Pulse Width Modulation ◽  
Multilevel Inverter ◽  
Multilevel Inverters ◽  
Modulation Technique ◽  
Three Phase ◽  
Field Programmable ◽  
Load Simulation ◽  
Sinusoidal Pulse Width Modulation

<p>Multilevel inverters (MLI) are becoming more popular over the years for medium and high power applications because of its significant merits over two level inverters. This paper presents an implementation of multicarrier based sinusoidal pulse width modulation technique for three phase seven level diode clamped multilevel inverter.  This topology is operated under phase opposition disposition pulse width modulation technique. The performance of three phase seven level diode clamped inverter is analyzed for induction motor (IM) load.  Simulation is performed using MATLAB/SIMULINK. Experimental results are presented to validate the effectiveness of the operation of the diode clamped multilevel inverter using field programmable gate array.</p>

Sign in / Sign up

Export Citation Format

Share Document