scholarly journals ModelSim/Simulink Cosimulation and FPGA Realization of a Multiaxis Motion Controller

2015 ◽  
Vol 2015 ◽  
pp. 1-17 ◽  
Author(s):  
Ying-Shieh Kung ◽  
Jin-Mu Lin ◽  
Yu-Jen Chen ◽  
Hsin-Hung Chou

This paper is to implement a multiaxis servo controller and a motion trajectory planning within one chip. At first, SoPC (system on a programmable chip) technology which is composed of an Altera FPGA (field programmable gate arrays) chip and an embedded soft-core Nios II processor is taken as the development of a multiaxis motion control IC. The multiaxis motion control IC has two modules. The first module is Nios II processor which realizes the motion trajectory planning by software. It includes the step, circular, window, star, and helical motion trajectory. The second module presents a function of the multiaxis position/speed/current controller IP (intellectual property) by hardware. And VHDL (VHSIC Hardware Description Language) is applied to describe the multiaxis servo controller behavior. Before the FPGA realization, a cosimulation work by ModelSim/Simulink is applied to test the VHDL code. Then, this IP combined by Nios II processor will be downloaded to FPGA. Therefore, a fully digital multiaxis motion controller can be realized by a single FPGA chip. Finally, to verify the effectiveness and correctness of the proposed multiaxis motion control IP, a three-axis motion platform (XYZtable) is constructed and some experimental results are presented.

2013 ◽  
Vol 284-287 ◽  
pp. 1909-1913
Author(s):  
Hsin Hung Chou ◽  
Ying Shieh Kung ◽  
Tai Wei Tsui ◽  
Stone Cheng

The novel FPGA (Field Programmable Gate Arrays) can embed a processor to be an SoPC (System-on-a-Programmable-Chip) environment which allows user to design the applications by mixing hardware and software. Therefore, a motion control system of wafer-handling robot based on the SoPC technology is presented in this paper. In FPGA, it is consists of two modules. The first module is Nios II processor which is used to realize the motion trajectory planning and three-axis position/speed controllers by software. The program developed in Nios II processor uses C language. The second module is presented to implement three-axis current vector controllers by hardware, and VHDL (VHSIC Hardware Description Language) is applied to describe the controller behavior. Therefore, a fully digital motion controller for wafer-handling robot, such as three current vector controllers, three position/speed controller and one trajectory planning are all can implemented by a single FPGA chip. Finally, an experimental system constructed by an FPGA experimental board, one three-DOF wafer-handling robot, and three inverters is set up to demonstrate the correctness and effectiveness of the proposed SoPC-based motion control system of wafer-handling robot.


2013 ◽  
Vol 479-480 ◽  
pp. 607-611
Author(s):  
Chiu Keng Lai ◽  
Yaw Ting Tsao ◽  
Shou Liang Tsai ◽  
Wei Nan Chen

Since the Field Programmable Gate Arrays (FPGAs) with high density are available nowadays, systems with complex functions can be realized by FPGA in a single chip while they are usually traditionally implemented by several individual chips. In this research, the drives as well as motion controller are integrated and implemented on Altera Cyclone III FPGA. The system is also evaluated by applying it to a 3-axis motion platform driven by stepping motors. Finally, experimental results of current regulator and motion controller are shown to prove the validness.


2012 ◽  
Vol 542-543 ◽  
pp. 573-577
Author(s):  
Ji Zeng Zhao ◽  
Min Xu ◽  
Wei Fu

This paper presents a method using the PCI motion controller which provides function of space linear interpolation to implement space arc trajectory planning on three dimensional motion platform. While make plane constraint to space spherical, we get space arc trajectory in Cartesian Coordinate System. Using the constraint arc by appropriate of precision discrete, function of space linear interpolation and the movement buffer nested in controller card to implement space arc movement. Writing control interface by using VC++ and actually validated on XYZ-three dimensional motion platform. The result confirmed feasibility and accuracy of this method.


2014 ◽  
Vol 6 ◽  
pp. 813204
Author(s):  
Chiu-Keng Lai ◽  
Yaw-Ting Tsao ◽  
Shou-Liang Tsai ◽  
Wei-Nan Chien

Since the Field Programmable Gate Arrays (FPGAs) with high density are available nowadays, systems with complex functions can thus be realized by FPGA in a single chip while they are traditionally implemented by several individual chips. In this research, the control of stepping motor drives as well as motion controller is integrated and implemented on Altera Cyclone III FPGA; the resulting system is evaluated by applying it to a 3-axis caving machine which is driven by stepping motors. Finally, the experimental results of current regulation and motion control integrated in FPGA IC are shown to prove the validness.


IEEE Access ◽  
2021 ◽  
pp. 1-1
Author(s):  
Alejandro GutierreznGiles ◽  
Luis U. EvangelistanHernandez ◽  
Marco A. Arteaga ◽  
Carlos A. CruznVillar ◽  
Alejandro RodrigueznAngeles

Author(s):  
A. Meghdari ◽  
H. Sayyaadi

Abstract An optimization technique based on the well known Dynamic Programming Algorithm is applied to the motion control trajectories and path planning of multi-jointed fingers in dextrous hand designs. A three fingered hand with each finger containing four degrees of freedom is considered for analysis. After generating the kinematics and dynamics equations of such a hand, optimum values of the joints torques and velocities are computed such that the finger-tips of the hand are moved through their prescribed trajectories with the least time or/and energy to reach the object being grasped. Finally, optimal as well as feasible solutions for the multi-jointed fingers are identified and the results are presented.


Author(s):  
Chan Boon Cheng ◽  
Asral Bahari Jambek

The implementation of a camera system with a field programmable gate array (FPGA) is an important step within research towards constructing a video processing architecture design based on FPGA. This paper presents the design and implementation of a camera system using the Nios II soft-core embedded processor from Altera. The proposed camera system is a flexible platform for the implementation of other systems such as image processing and video processing. The system architecture is designed using the Quartus II SOPC Builder System and implemented on an Altera DE2-70 development platform. The image or video is captured using a Terasic TRDB-D5M camera and stored into two different synchronous dynamic random access memories (SDRAM) using an SDRAM Controller. The specifications of the Terasic TRDB-D5M and SDRAM are examined to confirm that the recorded and stored data match. The results of this experiment show that the system is able to record and store data correctly into SDRAM. The data in the SDRAM correctly displays the recorded image on a VGA monitor.


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