scholarly journals Analytical Study on the Influence of Parasitic Elements in a Memristor

2018 ◽  
Vol 2018 ◽  
pp. 1-7
Author(s):  
Kristopher J. Chandía ◽  
Mauro Bologna ◽  
Bernardo Tellini
Keyword(s):  
Hysteresis Loop ◽  
Analytical Study ◽  
Multiple Scale ◽  
Intersection Point ◽  
Operating Frequency ◽  
Analytical Expression ◽  
Functional Behavior ◽  
Pinched Hysteresis Loop ◽  
Pinched Hysteresis ◽  
Scale Scheme

We study a memristive circuit with included parasitic elements, such as capacitance and inductance. In the multiple-scale scheme, we analytically show how the parasitic elements affect the voltage and the current. Finally, we provide an analytical expression for the intersection point coordinates, through which we discuss the functional behavior of the pinched hysteresis loop versus the operating frequency and the parasitic elements.

scholarly journals CMOS Realization of All-Positive Pinched Hysteresis Loops

Complexity ◽  
2017 ◽  
Vol 2017 ◽  
pp. 1-15 ◽  
Author(s):  
B. J. Maundy ◽  
A. S. Elwakil ◽  
C. Psychalinos
Keyword(s):  
Hysteresis Loop ◽  
Detailed Analysis ◽  
Hysteresis Loops ◽  
Nonlinear Circuits ◽  
Experimental Results ◽  
First Order ◽  
Pinched Hysteresis Loop ◽  
A Charge ◽  
Pinched Hysteresis ◽  
Nmos Transistors

Two novel nonlinear circuits that exhibit an all-positive pinched hysteresis loop are proposed. These circuits employ two NMOS transistors, one of which operates in its triode region, in addition to two first-order filter sections. We show the equivalency to a charge-controlled resistance (memristance) in a decremental state via detailed analysis. Simulation and experimental results verify the proposed theory.

A Novel Floating/Grounded Meminductor Emulator

2020 ◽  
Vol 29 (15) ◽  
pp. 2050247 ◽  
Author(s):  
Hasan Sozen ◽  
Ugur Cam
Keyword(s):  
Hysteresis Loop ◽  
Operational Amplifier ◽  
Current Conveyors ◽  
Current Feedback ◽  
Transconductance Amplifier ◽  
Additional Control ◽  
Pinched Hysteresis Loop ◽  
Terminal Element ◽  
Current Feedback Operational Amplifier ◽  
Pinched Hysteresis

Meminductor is a nonlinear two-terminal element with storage energy and memory ability. To date, meminductor element is not available commercially as memristor and memcapacitor are. Therefore, it is of great significance to implement a meminductor emulator for breadboard experiment. In this paper, a flux-controlled floating/grounded meminductor emulator without a memristor is presented. It is built with commercially available off-the-shelf electronic devices. It consists of single operational transconductance amplifier (OTA), single multiplier, two second-generation current conveyors (CCIIs), single current-feedback operational amplifier (CFOA) and single operational amplifier. Using OTA device introduces an additional control parameter besides frequency and amplitude values of applied voltage to control the area of pinched hysteresis loop of meminductor. Mathematical model of proposed emulator circuit is given to describe the behavior of meminductor circuit. The breadboard experiment is performed using CA3080, AD844, AD633J and LM741 for OTA, CCII–CFOA, multiplier and operational amplifier, respectively. Simulation and experimental test results are given to verify the theoretical analyses. Frequency-dependent pinched hysteresis loop is maintained up to 5 kHz. The presented meminductor emulator tends to work as ordinary inductor for higher frequencies.

Computation of the Area of Memristor Pinched Hysteresis Loop

2012 ◽  
Vol 59 (9) ◽  
pp. 607-611 ◽  
Author(s):  
Zdeněk Biolek ◽  
Dalibor Biolek ◽  
Viera Biolkova
Keyword(s):  
Hysteresis Loop ◽  
Pinched Hysteresis Loop ◽  
Pinched Hysteresis

Computing Areas of Pinched Hysteresis Loops of Mem-Systems in OrCAD PSPICE

2013 ◽  
Vol 278-280 ◽  
pp. 1081-1090 ◽  
Author(s):  
Dalibor Biolek ◽  
Zdenek Biolek ◽  
Viera Biolkova ◽  
Zdenek Kolka
Keyword(s):  
Hysteresis Loop ◽  
Memory Effect ◽  
Hysteresis Loops ◽  
Simulation Software ◽  
Excitation Signal ◽  
Pspice Simulation ◽  
Special Cases ◽  
Special Measuring ◽  
Pinched Hysteresis Loop ◽  
Pinched Hysteresis

The pinched hysteresis loop belongs to the fingerprints of the so-called mem-systems, their well-known special cases being memristors. The memory effect of the system is determined by the area of the curve lobes which gradually decrease with increasing repeating frequency of the excitation signal. The paper describes a method for automated computation of the above areas via the commonly utilized OrCAD PSpice simulation software with the help of special measuring functions of the PROBE postprocessor. The usefulness of the method is illustrated on an example of the analysis of a TiO2 memristor.

A New Floating Memristance Simulator Circuit Based on Second Generation Current Conveyor

2016 ◽  
Vol 26 (02) ◽  
pp. 1750029 ◽  
Author(s):  
Zehra Gulru Cam ◽  
Herman Sedef
Keyword(s):  
Hysteresis Loop ◽  
Second Generation ◽  
Current Conveyor ◽  
Experimental Results ◽  
Current Conveyors ◽  
Frequency Range ◽  
Passive Element ◽  
Exciting Frequency ◽  
Pinched Hysteresis Loop ◽  
Pinched Hysteresis

In this paper, a new floating analog memristance simulator circuit based on second generation current conveyors and passive elements is proposed. Theoretical derivations are presented which decribe the circuit characteristics. The hardware of proposed simulator circuit is built using commercially available components. Theoretical derivations are validated with PSPICE simulation and experimental results. Performance of circuit was tested with simple example circuits. All results show that proposed simulator circuit provides frequency dependent pinched hysteresis loop and nonvolatility features. Exciting frequency, minimum and maximum memristance values and memristance range can be adjustable with simple passive element values. Simulator circuit has a frequency range of 1[Formula: see text]Hz to 40[Formula: see text]kHz.

scholarly journals Pinched hysteresis loop in defect-free ferroelectric materials

2016 ◽  
Vol 94 (14) ◽  
Author(s):  
Bin Xu ◽  
Charles Paillard ◽  
Brahim Dkhil ◽  
L. Bellaiche
Keyword(s):  
Hysteresis Loop ◽  
Ferroelectric Materials ◽  
Pinched Hysteresis Loop ◽  
Pinched Hysteresis

Novel design for the odd-symmetric memristor from asymmetric switches

2015 ◽  
Vol 3 (12) ◽  
pp. 2768-2772 ◽  
Author(s):  
Peifu Cheng ◽  
Yun Hang Hu
Keyword(s):  
Hysteresis Loop ◽  
Pinched Hysteresis Loop ◽  
Novel Strategy ◽  
Pinched Hysteresis ◽  
Novel Design

A novel strategy, in which two same asymmetric A/B structure switch components can be combined as a symmetric A/B/A structured device, is developed to create an odd-symmetric memristor. Furthermore, the feasibility of this strategy is experimentally confirmed by a Ag2S/Ag/Ag2S memristor, which exhibits an odd-symmetric I–V curve with a pinched hysteresis loop.

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