scholarly journals A High-Performance Elliptic Curve Cryptographic Processor of SM2 over GF(p)

Electronics ◽  
2019 ◽  
Vol 8 (4) ◽  
pp. 431 ◽  
Author(s):  
Xianghong Hu ◽  
Xin Zheng ◽  
Shengshi Zhang ◽  
Weijun Li ◽  
Shuting Cai ◽  
...  
Keyword(s):  
Elliptic Curve ◽  
High Performance ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Prime Field ◽  
Practical Applications ◽  
Public Key Cryptosystems ◽  
Cell Library ◽  
Multiplication Operation ◽  
And Performance

Elliptic curve cryptography (ECC) is widely used in practical applications because ECC has far fewer bits for operands at the same level of security than other public-key cryptosystems such as RSA. The performance of an ECC processor is usually determined by modular multiplication (MM) and point multiplication (PM) operations. For recommended prime field, MM operation can consist of multiplication and fast reduction operations. In this paper, a 256-bit multiplication operation is implemented by a 129-bit (half-word) multiplier using Karatsuba–Ofman multiplication algorithm. The fast reduction is a modulo operation, which gets 512-bit input data from multiplication and outputs a 256-bit result ( 0 ≤ Z < p ) . We propose a two-stage fast reduction algorithm (TSFR) over SCA-256 prime field, which can obtain an intermediate result of 0 ≤ Z < 2 p instead of 0 ≤ Z < 14 p in traditional algorithm, avoiding a lot of repetitive subtraction operations. The PM operation is implemented in width nonadjacent form (NAF) algorithm and its operational schedules are improved to increase the parallelism of multiplication and fast reduction operations. Synthesized with a 0.13 μ m complementary metal oxide semiconductor (CMOS) standard cell library, the proposed processor costs an area of 280 k gates and PM operation takes 0.057 ms at the frequency of 250 MHz. The design is also implemented on Xilinx Virtex-6 platform, which consumes 27.655 k LUTs and takes 0.37 ms to perform one 256-bit PM operation, attaining six times speed-up over the state-of-the-art. The processor makes a tradeoff between area and performance, thus it is better than other methods.

scholarly journals A High-Speed Elliptic Curve Cryptography Processor for Teleoperated Systems Security

2021 ◽  
Vol 2021 ◽  
pp. 1-8
Author(s):  
Yong Xiao ◽  
Weibin Lin ◽  
Yun Zhao ◽  
Chao Cui ◽  
Ziwen Cai
Keyword(s):  
Elliptic Curve ◽  
Elliptic Curve Cryptography ◽  
High Speed ◽  
High Performance ◽  
Prime Field ◽  
Practical Applications ◽  
Cell Library ◽  
Cryptographic Algorithm ◽  
Human Operators ◽  
Key Length

Teleoperated robotic systems are those in which human operators control remote robots through a communication network. The deployment and integration of teleoperated robot’s systems in the medical operation have been hampered by many issues, such as safety concerns. Elliptic curve cryptography (ECC), an asymmetric cryptographic algorithm, is widely applied to practical applications because its far significantly reduced key length has the same level of security as RSA. The efficiency of ECC on GF (p) is dictated by two critical factors, namely, modular multiplication (MM) and point multiplication (PM) scheduling. In this paper, the high-performance ECC architecture of SM2 is presented. MM is composed of multiplication and modular reduction (MR) in the prime field. A two-stage modular reduction (TSMR) algorithm in the SCA-256 prime field is introduced to achieve low latency, which avoids more iterative subtraction operations than traditional algorithms. To cut down the run time, a schedule is put forward when exploiting the parallelism of multiplication and MR inside PM. Synthesized with a 0.13 um CMOS standard cell library, the proposed processor consumes 341.98k gate areas, and each PM takes 0.092 ms.

scholarly journals Design and Implementation of High Performance and Low Power Mixed Logic Line Decoders

2019 ◽  
Vol 8 (6S4) ◽  
pp. 635-640
Keyword(s):  
High Performance ◽  
Data Transfer ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Oxide Semiconductor ◽  
Analog To Digital ◽  
Delay Performance ◽  
And Performance ◽  
Almost All

The decoders are widely used in the logical circuits, data transfer circuits and analog to digital conversions. A mixed logic design methods for the line decoders are used to combining the transmission gate logic, pass transistor logic, and complementary metal-oxide semiconductor (CMOS) technology provides desired operation and performance. A novel topology is presented for the 2 to 4 decoder requires a fourteen transistor topology aiming on reducing the transistor count and operating power and a fifteen transistor topology aiming on high power and low delay performance. The standard and inverting decoders are designed in each of the case, gives a total of four new designs circuits. All the proposed decoders have compact transistor count compared to their conservative CMOS technologies. Finally, a variety of proposed designs present a noteworthy improvement in operating power and propagation delay, outperforming CMOS in almost all the cases.

scholarly journals Ab initio perspective of ultra-scaled CMOS from 2D-material fundamentals to dynamically doped transistors

2021 ◽  
Vol 5 (1) ◽  
Author(s):  
Aryan Afzalian
Keyword(s):  
Field Effect ◽  
High Performance ◽  
Field Effect Transistor ◽  
High Mobility ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Grand Challenge ◽  
Gate Length ◽  
Delay Performance ◽  
Effect Transistor

AbstractUsing accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10-nm scaling for high-performance complementary metal oxide semiconductor (CMOS) applications. We show that a combination of good electrostatic control together with high mobility is paramount to meet the stringent roadmap targets. Such requirements typically play against each other at sub-10-nm gate length for MOS transistors made of conventional semiconductor materials like Si, Ge, or III–V and dimensional scaling is expected to end ~12 nm gate-length (pitch of 40 nm). We demonstrate that using alternative 2D channel materials, such as the less-explored HfS2 or ZrS2, high-drive current down to ~6 nm is, however, achievable. We also propose a dynamically doped field-effect transistor concept, that scales better than its MOSFET counterpart. Used in combination with a high-mobility material such as HfS2, it allows for keeping the stringent high-performance CMOS on current and competitive energy-delay performance, when scaling down to virtually 0 nm gate length using a single-gate architecture and an ultra-compact design (pitch of 22 nm). The dynamically doped field-effect transistor further addresses the grand-challenge of doping in ultra-scaled devices and 2D materials in particular.

Characterization of High-Performance Polycrystalline Silicon Complementary Metal–Oxide–Semiconductor Circuits

2007 ◽  
Vol 46 (1) ◽  
pp. 51-55 ◽  
Author(s):  
Genshiro Kawachi ◽  
Yoshiaki Nakazaki ◽  
Hiroyuki Ogawa ◽  
Masayuki Jyumonji ◽  
Noritaka Akita ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Polycrystalline Silicon ◽  
High Performance ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Semiconductor Circuits

scholarly journals Performance Measures of Different Gate Oxide Materials in Gate All Around Fet

2020 ◽  
Vol 9 (2) ◽  
pp. 23-25
Keyword(s):  
High Performance ◽  
Field Effect Transistors ◽  
Gate Oxide ◽  
Oxide Semiconductor ◽  
Oxide Materials ◽  
Performance Limits ◽  
Short Channel ◽  
Advanced Technique ◽  
And Performance

The classical planar Metal Oxide Semiconductor Field Effect Transistors (MOSFET) is fabricated by oxidation of a semiconductor namely Silicon. In this generation, an advanced technique called 3D system architecture FETs, are introduced for high performance and low power quality of devices. Based on the limitations of Short Channel Effect (SCE), Silicon (Si) FET cannot be scaled under 10nm. Hence various performing measures like methods, principles, and geometrics are done to upscale the semiconductor. CMOS using alternate channel materials like GE and III-Vs on substrates is a highly anticipated technique for developing nanowire structures. By considering these issues, in this paper, we developed a simulation model that provides accurate results basing on Gate layout and multi-gate NW FET's so that the scaling can be increased few nanometers long and performance limits gradually increases. The model developed is SILVACO that tests the action of FET with different gate oxide materials.

scholarly journals A Multiplexed Chemical Sensing CMOS Imager

2021 ◽  
Author(s):  
Di Wang ◽  
Fenni Zhang ◽  
Kyle Mallires ◽  
Vishal Tipparaju ◽  
Jingjing Yu ◽  
...  
Keyword(s):  
Chemical Sensing ◽  
High Performance ◽  
Health Management ◽  
Complementary Metal Oxide Semiconductor ◽  
Spot Size ◽  
Oxide Semiconductor ◽  
Colorimetric Sensing ◽  
Widespread Application ◽  
Cmos Imager ◽  
Cmos Chip

Abstract A miniaturized and multiplexed chemical sensing technology is urgently needed to empower mobile devices, Internet-of-Things (IoTs) and robots for various new applications. Here, we show that a complementary metal-oxide-semiconductor (CMOS) imager can be turned into a multiplexed colorimetric sensing chip by coating micron-scale colorimetric sensing spots on the imager surface. Each sensing spot contains chemical sensing materials and nanoparticles for colorimetric signal enhancement. The sensitivity is spot-size invariant, and high-performance chemical sensing can be achieved on sensing spot as small as ~ 10 µm. This great scalability combined with millions of pixels of a CMOS imager offers a promising platform for highly integrated chemical sensors. Moreover, the chemical CMOS chip can be readily integrated with mobile electronics. As a proof-of-concept, we have built a smartphone accessary based on this chemical CMOS chip for personal health management. We anticipate that this new platform will pave the way for the widespread application of chemical sensing, such as mobile health (mHealth), IoTs, electronic nose, and smart homes.

The Effect of Strain on the Formation of Dislocations at the SiGe/Si Interface

MRS Bulletin ◽  
1996 ◽  
Vol 21 (4) ◽  
pp. 38-44 ◽  
Author(s):  
F.K. LeGoues
Keyword(s):  
Metal Oxide ◽  
High Speed ◽  
High Performance ◽  
Field Effect Transistors ◽  
Low Cost ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Design Rule ◽  
Strained Si

Recently much interest has been devoted to Si-based heteroepitaxy, and in particular, to the SiGe/Si system. This is mostly for economical reasons: Si-based technology is much more advanced, is widely available, and is cheaper than GaAs-based technology. SiGe opens the door to the exciting (and lucrative) area of Si-based high-performance devices, although optical applications are still limited to GaAs-based technology. Strained SiGe layers form the base of heterojunction bipolar transistors (HBTs), which are currently used in commercial high-speed analogue applications. They promise to be low-cost compared to their GaAs counterparts and give comparable performance in the 2-20-GHz regime. More recently we have started to investigate the use of relaxed SiGe layers, which opens the door to a wider range of application and to the use of SiGe in complementary metal oxide semiconductor (CMOS) devices, which comprise strained Si and SiGe layers. Some recent successes include record-breaking low-temperature electron mobility in modulation-doped layers where the mobility was found to be up to 50 times better than standard Si-based metal-oxide-semiconductor field-effect transistors (MOSFETs). Even more recently, SiGe-basedp-type MOSFETS were built with oscillation frequency of up to 50 GHz, which is a new record, in anyp-type material for the same design rule.

Analysis and Simulation of a Low-Leakage Analog Single Gate and FinFET Circuits

2014 ◽  
Vol 13 (02) ◽  
pp. 1450012 ◽  
Author(s):  
Manorama Chauhan ◽  
Ravindra Singh Kushwah ◽  
Pavan Shrivastava ◽  
Shyam Akashe
Keyword(s):  
Integrated Circuits ◽  
Metal Oxide ◽  
Low Power ◽  
High Performance ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Short Channel ◽  
State Dependency ◽  
Low Leakage

In the world of Integrated Circuits, complementary metal–oxide–semiconductor (CMOS) has lost its ability during scaling beyond 50 nm. Scaling causes severe short channel effects (SCEs) which are difficult to suppress. FinFET devices undertake to replace usual Metal Oxide Semiconductor Field Effect Transistor (MOSFETs) because of their better ability in controlling leakage and diminishing SCEs while delivering a strong drive current. In this paper, we present a relative examination of FinFET with the double gate MOSFET (DGMOSFET) and conventional bulk Si single gate MOSFET (SGMOSFET) by using Cadence Virtuoso simulation tool. Physics-based numerical two-dimensional simulation results for FinFET device, circuit power is presented, and classifying that FinFET technology is an ideal applicant for low power applications. Exclusive FinFET device features resulting from gate–gate coupling are conversed and efficiently exploited for optimal low leakage device design. Design trade-off for FinFET power and performance are suggested for low power and high performance applications. Whole power consumptions of static and dynamic circuits and latches for FinFET device, believing state dependency, show that leakage currents for FinFET circuits are reduced by a factor of over ~ 10X, compared to DGMOSFET and ~ 20X compared with SGMOSFET.

Analog Complementary Metal–Oxide–Semiconductor Integrate-and-Fire Neuron Circuit for Overflow Retaining in Hardware Spiking Neural Networks

2020 ◽  
Vol 20 (5) ◽  
pp. 3117-3122
Author(s):  
Sungmin Hwang ◽  
Jeong-Jun Lee ◽  
Min-Woo Kwon ◽  
Myung-Hyun Baek ◽  
Taejin Jang ◽  
...  
Keyword(s):  
Neural Network ◽  
High Performance ◽  
Single Layer ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Basic Operation ◽  
Neuron Circuit ◽  
Integrate And Fire ◽  
Analog Cmos ◽  
High Level

The spiking neural network (SNN) is regarded as the third generation of an artificial neural network (ANN). In order to realize a high-performance SNN, an integrate-and-fire (I&F) neuron, one of the key elements in an SNN, must retain the overflow in its membrane after firing. This paper presents an analog CMOS I&F neuron circuit for overflow retaining. Compared with the conventional I&F neuron circuit, the basic operation of the proposed circuit is confirmed in a circuit-level simulation. Furthermore, a single-layer SNN simulation was also performed to demonstrate the effect of the proposed circuit on neural network applications by comparing the raster plots from the circuit-level simulation with those from a high-level simulation. These results demonstrate the potential of the I&F neuron circuit with overflow retaining characteristics to be utilized in upcoming high-performance hardware SNN systems.

Electromechanical Computing at 500°C with Silicon Carbide

Science ◽  
2010 ◽  
Vol 329 (5997) ◽  
pp. 1316-1318 ◽  
Author(s):  
Te-Hao Lee ◽  
Swarup Bhunia ◽  
Mehran Mehregany
Keyword(s):  
Silicon Carbide ◽  
Thermal Management ◽  
High Performance ◽  
Field Effect Transistors ◽  
Complementary Metal Oxide Semiconductor ◽  
Logic Circuits ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Propulsion Systems ◽  
Heat Sinking

Logic circuits capable of operating at high temperatures can alleviate expensive heat-sinking and thermal-management requirements of modern electronics and are enabling for advanced propulsion systems. Replacing existing complementary metal-oxide semiconductor field-effect transistors with silicon carbide (SiC) nanoelectromechanical system (NEMS) switches is a promising approach for low-power, high-performance logic operation at temperatures higher than 300°C, beyond the capability of conventional silicon technology. These switches are capable of achieving virtually zero off-state current, microwave operating frequencies, radiation hardness, and nanoscale dimensions. Here, we report a microfabricated electromechanical inverter with SiC complementary NEMS switches capable of operating at 500°C with ultralow leakage current.

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