scholarly journals A Hardware-Efficient Elliptic Curve Cryptographic Architecture over GF (p)

2021 ◽  
Vol 2021 ◽  
pp. 1-7
Author(s):  
Chao Cui ◽  
Yun Zhao ◽  
Yong Xiao ◽  
Weibin Lin ◽  
Di Xu
Keyword(s):  
Elliptic Curve ◽  
Elliptic Curve Cryptography ◽  
Scalar Multiplication ◽  
Time Range ◽  
Modular Multiplication ◽  
Hardware Resource ◽  
Data Register

This paper proposes a hardware-efficient elliptic curve cryptography (ECC) architecture over GF(p), which uses adders to achieve scalar multiplication (SM) through hardware-reuse method. In terms of algorithm, the improvement of the interleaved modular multiplication (IMM) algorithm and the binary modular inverse (BMI) algorithm needs two adders. In addition to the adder, the data register is another optimize target. The design compiler is synthesized on 0.13 µm CMOS ASIC platform. The time range of performing scalar multiplication over 160, 192, 224, and 256 field orders under 150 MHz frequency is 1.99–3.17 ms. Moreover, the gate area required for different field orders in this design is in the range of 35.65k–59.14k, with 50%–91% hardware resource less than other processors.

scholarly journals Fast Implementation of NIST P-256 Elliptic Curve Cryptography on 8-Bit AVR Processor

2020 ◽  
Vol 10 (24) ◽  
pp. 8816
Author(s):  
Dong-won Park ◽  
Nam Su Chang ◽  
Sangyub Lee ◽  
Seokhie Hong
Keyword(s):  
Elliptic Curve ◽  
Elliptic Curve Cryptography ◽  
Execution Time ◽  
State Of The Art ◽  
Optimization Technique ◽  
Scalar Multiplication ◽  
Modular Multiplication ◽  
Avr Microcontroller ◽  
High Degree ◽  
The Impact

In this paper, we present a highly optimized implementation of elliptic curve cryptography (ECC) over NIST P-256 curve for an 8-bit AVR microcontroller. For improving the performance of ECC implementation, we focus on optimizing field arithmetics. In particular, we optimize the modular multiplication and squaring method exploiting the state-of-the-art optimization technique, namely range shifted representation (RSR). With optimized field arithmetics, we significantly improve the performance of scalar multiplication and set the speed record for execution time of variable base scalar multiplication over NIST P-256 curve. When compared with previous works, we achieve a performance gain of 17.3% over the best previous result on the same platform. Moreover, the execution time of our result is even faster than that over the NIST P-192 curve of the well-known TinyECC library. Our result shows that RSR can be applied to all field arithmetics and evaluate the impact of the adoption of RSR over the performance of scalar multiplication. Additionally, our implementation provides a high degree of regularity to withstand side-channel attacks.

scholarly journals Efficient implementation of modular multiplication over 192-bit NIST prime for 8-bit AVR-based sensor node

2020 ◽  
Author(s):  
Dong-won Park ◽  
Seokhie Hong ◽  
Nam Su Chang ◽  
Sung Min Cho
Keyword(s):  
Elliptic Curve ◽  
Elliptic Curve Cryptography ◽  
Sensor Node ◽  
Efficient Implementation ◽  
Memory Access ◽  
Modular Multiplication ◽  
Reduction Operation ◽  
Computational Overhead ◽  
Integer Representation ◽  
Constrained Devices

Abstract Modular multiplication is one of the most time-consuming operations that account for almost 80% of computational overhead in a scalar multiplication in elliptic curve cryptography. In this paper, we present a new speed record for modular multiplication over 192-bit NIST prime P-192 on 8-bit AVR ATmega microcontrollers. We propose a new integer representation named Range Shifted Representation (RSR) which enables an efficient merging of the reduction operation into the subtractive Karatsuba multiplication. This merging results in a dramatic optimization in the intermediate accumulation of modular multiplication by reducing a significant amount of unnecessary memory access as well as the number of addition operations. Our merged modular multiplication on RSR is designed to have two duplicated groups of 96-bit intermediate values during accumulation. Hence, only one accumulation of the group is required and the result can be used twice. Consequently, we significantly reduce the number of load/store instructions which are known to be one of the most time-consuming operations for modular multiplication on constrained devices. Our implementation requires only 2888 cycles for the modular multiplication of 192-bit integers and outperforms the previous best result for modular multiplication over P-192 by a factor of 17%. In addition, our modular multiplication is even faster than the Karatsuba multiplication (without reduction) which achieved a speed record for multiplication on AVR processor.

Secure and Robust Telemedicine using ECC on Radix-8 with Formal Verification

2021 ◽  
pp. 573-590
Author(s):  
Gautam Kumar ◽  
Hemraj Saini
Keyword(s):  
Computational Complexity ◽  
Elliptic Curve ◽  
Formal Verification ◽  
Elliptic Curve Cryptography ◽  
Clock Cycle ◽  
Scalar Multiplication ◽  
Efficient Technique ◽  
Computation Efficiency ◽  
Research Gap ◽  
Hardware Performance

The scalar multiplication techniques used in Elliptic curve cryptography (ECC) are having the scope for gaining the computation efficiency. This is possible through the reduction of precomputed operations. Finding the more efficient technique compares to the most recent or efficient one is a research gap for all schemes. The manuscript presents an application oriented work for Telemedicine using ECC. It is based on robust application on reduced computational complexity. The methodology we apply for the same is Scalar Multiplication without precomputation on Radix-8. Introduced software and the hardware performance are reporting a big advantage over all the related proposed techniques. The reason to cover this problem is to provide a path on a fascinating area of ECC on a smaller key size be applicable for all applications on a same level of security strengths. The smaller length key gives the higher speed and shorter clock cycle to initiate the operation.

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