scholarly journals Performance Analysis of Mesh-based NoC’s on Routing Algorithms

2018 ◽  
Vol 8 (5) ◽  
pp. 3368
Author(s):  
Anala M. R ◽  
Amit N. Subrahmanya ◽  
Allbright D’Souza
Keyword(s):  
Communication Systems ◽  
Routing Algorithm ◽  
Network On Chip ◽  
Routing Algorithms ◽  
Mesh Network ◽  
Traffic Patterns ◽  
Routing Strategy ◽  
On Chip ◽  
Point To Point

The advent of System-on-Chip (SoCs), has brought about a need to increase the scale of multi-core chip networks. Bus Based communications have proved to be limited in terms of performance and ease of scalability, the solution to both bus – based and Point-to-Point (P2P) communication systems is to use a communication infrastructure called Network-on-Chip (NoC). Performance of NoC depends on various factors such as network topology, routing strategy and switching technique and traffic patterns. In this paper, we have taken the initiative to compile together a comparative analysis of different Network on Chip infrastructures based on the classification of routing algorithm, switching technique, and traffic patterns. The goal is to show how varied combinations of the three factors perform differently based on the size of the mesh network, using NOXIM, an open source SystemC Simulator of mesh-based NoC. The analysis has shown tenable evidence highlighting the novelty of XY routing algorithm.

Comparative Performance Analysis of 
Selected Routing Algorithms by Load Variation of 2-Dimensional Mesh Topology Based 
Network-On-Chip

2021 ◽  
Vol 20 (3) ◽  
pp. 1-6
Author(s):  
Mohammed Shaba Saliu ◽  
Muyideen Omuya Momoh ◽  
Pascal Uchenna Chinedu ◽  
Wilson Nwankwo ◽  
Aliu Daniel
Keyword(s):  
Routing Algorithm ◽  
Adaptive Routing ◽  
Injection Rate ◽  
Network On Chip ◽  
Routing Algorithms ◽  
Comparative Performance ◽  
Traffic Pattern ◽  
Mesh Topology ◽  
Similar Vein ◽  
On Chip

Network-on-Chip (NoC) has been proposed as a viable solution to the communication challenges on System-on-Chips (SoCs). As the communication paradigm of SoC, NoCs performance depends mainly on the type of routing algorithm chosen. In this paper different categories of routing algorithms were compared. These include XY routing, OE turn model adaptive routing, DyAD routing and Age-Aware adaptive routing.  By varying the load at different Packet Injection Rate (PIR) under random traffic pattern, comparison was conducted using a 4 × 4 mesh topology. The Noxim simulator, a cycle accurate systemC based simulator was employed. The packets were modeled as a Poisson distribution; first-in-first-out (FIFO) input buffer channel with a depth of five (5) flits and a flit size of 32 bits; and a packet size of 3 flits respectively. The simulation time was 10,000 cycles. The findings showed that the XY routing algorithm performed better when the PIR is low.  In a similar vein, the DyAD routing and Age-aware algorithms performed better when the load i.e. PIR is high.

Probabilistic odd–even: an adaptive wormhole routing algorithm for 2D mesh network-on-chip

2014 ◽  
Vol 70 (1) ◽  
pp. 385-407 ◽  
Author(s):  
Su Hu ◽  
Wenzheng Xu ◽  
Jing Lin ◽  
Xiaola Lin
Keyword(s):  
Routing Algorithm ◽  
Network On Chip ◽  
Wormhole Routing ◽  
Mesh Network ◽  
On Chip

A Fault-Tolerant Routing Algorithm Using Tunnels in Fault Blocks for Network-on-Chip

2017 ◽  
Vol 27 (02) ◽  
pp. 1850022 ◽  
Author(s):  
Ling Wang ◽  
Terrence Mak
Keyword(s):  
Fault Tolerant ◽  
Routing Algorithm ◽  
Network On Chip ◽  
Mesh Network ◽  
Communication Performance ◽  
Simulation Results ◽  
On Chip

In 2D mesh Network on Chips (NoCs), fault-tolerant algorithms usually deactivate healthy nodes to form rectangular or convex fault blocks. However, the deactivated nodes can possibly form an available tunnel in a faulty block. We propose a method to discover these tunnels, and propose a fault-tolerant routing algorithm to route messages through such paths such that the overall communication performance is improved. In addition, the algorithm is deadlock-free by prohibiting some turns. Simulation results demonstrate that the reuse of the sacrificed nodes in fault blocks can significantly reduce the average message latency.

scholarly journals Age-aware Adaptive Routing for Network-on-Chip Routing with Odd-Even Turn Model

2020 ◽  
Vol 4 (2) ◽  
Author(s):  
M. S Saliu ◽  
I. J Umoh ◽  
B.O. Sadiq ◽  
M.O Momoh
Keyword(s):  
Performance Metrics ◽  
Routing Algorithm ◽  
Adaptive Routing ◽  
Network On Chip ◽  
Point Of View ◽  
Destination Node ◽  
Traffic Patterns ◽  
Average Latency ◽  
On Chip ◽  
High Degree

This paper presents an age-aware adaptive routing for Odd-Even (OE) turn model. As packets traverse from source to destination node, their paths are defined by a given routing algorithm. For a selected routing algorithm, an efficient arbitration technique is crucial to sharing critical Network-on-Chip resources. Arbitration techniques provide high degree of local fairness from each router point of view. However, there is delay of a packet with a longer path between the source and destination nodes. In order to address this challenge an age-based arbitration technique is hereby proposed for adaptive routing with OE turn model. The age-aware adaptive routing uses an age-based arbitration technique that gives priority to oldest packet. The performance of the developed age-aware adaptive routing was evaluated using different synthetic traffic at different Packet Injection Rates (PIRs). Results were compared with the result obtained on fair arbitration technique for adaptive routing using average latency and throughput as performance metrics. The result indicated that the age-aware adaptive routing has 2.73%, 6.63 %,5.4% and 4.5 % reduction in latency under random, transpose 1 transpose 2 and bit reversal traffic patterns respectively when compared to fair arbitration adaptive routing with OE turn model. For throughput the results indicated that the age-aware adaptive routing with OE turn model has 14.22%, 13%.12% and 19% increase in throughput under random, transpose 1 transpose 2 and bit reversal traffic patterns respectively when compared to fair arbitration adaptive routing with OE turn model.

scholarly journals Congestion-Aware Routing Algorithm for NoC Using Data Packets

2021 ◽  
Vol 2021 ◽  
pp. 1-11
Author(s):  
Khurshid Ahmad ◽  
Muhammad Athar Javed Sethi ◽  
Rehmat Ullah ◽  
Imran Ahmed ◽  
Amjad Ullah ◽  
...  
Keyword(s):  
Routing Algorithm ◽  
Network On Chip ◽  
Routing Algorithms ◽  
System On Chip ◽  
Multiprocessor System ◽  
Data Packets ◽  
Communication Framework ◽  
Using Data ◽  
On Chip ◽  
Congestion Aware

Network on Chip (NoC) is a communication framework for the Multiprocessor System on Chip (MPSoC). It is a router-based communication system. In NoC architecture, nodes of MPSoC are communicating through the network. Different routing algorithms have been developed by researchers, e.g., XY, intermittent XY, DyAD, and DyXY. The main problems in these algorithms are congestion and faults. Congestion and faults cause delay, which degrades the performance of NoC. A congestion-aware algorithm is used for the distribution of traffic over NoC and for the avoidance of congestion. In this paper, a congestion-aware routing algorithm is proposed. The algorithm works by sending congestion information in the data packet. The algorithm is implemented on a 4 × 4 mesh NoC using FPGA. The proposed algorithm decreases latency, increases throughput, and uses less bandwidth in sharing congestion information between routers in comparison to the existing congestion-aware routing algorithms.

scholarly journals A New Efficient and Reliable Dynamically ReconfigurableNetwork-on-Chip

2012 ◽  
Vol 2012 ◽  
pp. 1-16 ◽  
Author(s):  
Cédric Killian ◽  
Camel Tanougast ◽  
Fabrice Monteiro ◽  
Abbas Dandache
Keyword(s):  
Error Detection ◽  
Routing Algorithm ◽  
Network On Chip ◽  
Routing Algorithms ◽  
Data Packet ◽  
Reliable Operation ◽  
Detection Mechanism ◽  
Dynamically Reconfigurable ◽  
On Chip ◽  
Online Error Detection

We present a new reliableNetwork-on-Chip(NoC) suitable forDynamically Reconfigurable Multiprocessors on Chipsystems. The proposedNoCis based on routers performing online error detection of routing algorithm and data packet errors. Our work focuses on adaptive routing algorithms which allow to bypass faulty components or processor elements dynamically implemented inside the network. The proposed routing error detection mechanism allows to distinguish routing errors from bypasses of faulty components. The new router architecture is based on additional diagonal state indications and specific logic blocks allowing the reliable operation of theNoC. The main originality in the proposedNoCis that only the permanently faulty parts of the routers are disconnected. Therefore, our approach maintains a high run time throughput in theNoCwithout data packet loss thanks to a self-loopbackmechanism inside each router.

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