scholarly journals Analysis of CMOS Logic and Transmission Gate for 64 Bit Parallel Prefix Adders

2018 ◽  
Vol 7 (2) ◽  
pp. 115
Author(s):  
Nehru.K K ◽  
Nagarjuna T ◽  
Somanaidu U
Keyword(s):  
High Performance ◽  
Digital Signal ◽  
Digital Signal Processors ◽  
Transmission Technique ◽  
Look Ahead ◽  
Parallel Prefix ◽  
Prefix Adder ◽  
Signal Processors ◽  
Prefix Adders ◽  
Better Than

<span>Parallel prefix adder network is a type of carry look ahead adder structure. It is widely considered as the fastest adder and used for high performance arithmetic circuits in the digital signal processors. In this article, an introduction to the design of 64 bit parallel prefix adder using transmission technique which acquires least no of nodes<strong> </strong>with the lowest transistor<strong> </strong>count and low power consumption is presented. The 64 bit parallel prefix adder is designed and comparison is made between other previously parallel prefix adders. The result shows that the proposed 64 bit parallel prefix adder is slightly better than existing parallel prefix adders and it considerably increases the computation speed.The spice tool is used for analysis with different supply voltages.</span>

scholarly journals Delay Efficient Vedic Multiplier for DSP

2019 ◽  
Vol 8 (9S) ◽  
pp. 499-501
Keyword(s):  
Digital Signal ◽  
Digital Signal Processors ◽  
Vedic Multiplier ◽  
Ripple Carry Adder ◽  
Parallel Prefix ◽  
Minimum Delay ◽  
Signal Processors ◽  
Prefix Adders ◽  
Dsp Applications

Multipliers are very essential blocks in any arithmetic and logic unit, accumulators and Digital signal processors. Due to the enlarging check on delay, design of faster multipliers is desired. Amidst numerous multipliers, Vedic multipliers are favored for their speed of operation. There are sixteen sutras in Vedic mathematics out of which four are multiplication techniques. “URDHVA TIRYAKBHYAM” is the most efficient vedic multiplication technique in terms of speed. In this paper we aim to develop a multiplier using Ripple Carry Adder and parallel prefix adders which carry out the “URDHVA TIRYAKBHYAM” sutra with improved speed of operation by providing the minimum delay for the multiplication of numbers regardless of their bit sizes. A vast majority of the engineering domain consists of ubiquitous technologies like DSP. As it is one of the most rapid growing technologies of the 21st Century, it faces challenges and improvisation at each step. Engineers are working diligently to improve the quality of Digital Signal processors and major breakthroughs are being made at a very good rate. Proposed multiplier could be applied for such DSP applications. Verilog language has been used for the coding. Xilinx Vivado Tool is used for synthesis and Model Sim 5.4 has been used for simulation.

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