A 3D Simulation Based Study of Surface Potential for Cylindrical Gate (CG) MOSFETs

2015 ◽  
Vol 10 (5) ◽  
pp. 623-626
Author(s):  
Prince Kumar
2010 ◽  
Vol 99 (3) ◽  
pp. 237-251 ◽  
Author(s):  
Caroline Koh ◽  
Hock Soon Tan ◽  
Kim Cheng Tan ◽  
Linda Fang ◽  
Fook Meng Fong ◽  
...  

2003 ◽  
Vol 771 ◽  
Author(s):  
Keiji Sugi ◽  
Hisao Ishii ◽  
Yasuo Kimura ◽  
Michio Niwano ◽  
Naoki Hayashi ◽  
...  

AbstractRecently we found high and persistent spontaneous buildup of the surface potential upon vacuum vapor deposition of tris(8-hydroxyquinolinato) aluminum(III)(Alq3) on Au substrate under dark conditions (28 V for 560 nm thick Alq3 film). Such giant potential is removed by visible-light irradiation. These natures of the film suggest the possible applications to various organic devices such as memory devices. In this study, we investigated the retention time of the giant potential and the mechanism of the light-induced depolarization in order to discuss the feasibility of the device applications. The observed decay rate of the surface potential in vacuum condition was roughly 10 % loss in 10 years, which is enough for memory devices. As to the decay rate by light-irradiation, the observed rate was successfully reproduced by a theoretical simulation based on the photo-induced randomization of oriented Alq3 molecules.


2021 ◽  
Author(s):  
GIRDHAR GOPAL ◽  
Tarun varma

Abstract The Ultrathin body double gate FE layer TFET(UTB-DG-FE-TFET) is proposed and investigated in this work. Electrical performance parameters such as surface potential ψ(x), electrical field, drain current, sub-threshold swing, threshold voltage, and I on /I off ratio are further analyzed using simulation-based analysis. Integration of Si: HFO 2 ferroelectric layer on top and bottom surfaces make the structure that provides negative capacitance, higher on current, enormous surface potential, peak electric field, and improvement in SS with degradation in off Current. The suggested design is evaluated in comparison with FE-TFET and standard TFET devices. Finally, the impact of device geometry variants like ferroelectric layer thickness (t fe ), intrinsic channel thickness t si , interfacial layer types, interfacial layer thickness (t ox ) and channel length L c on transfer characteristics are investigated through 2D TCAD Sentaurus Simulator for a clear validation of its optimization. The recommended work demonstrates that it is a suitable device enabling superior performance and helpful in ultra-low-power applications.


Author(s):  
Zhengshu Shen ◽  
Jami J. Shah ◽  
Joseph K. Davidson

Development of tolerance analysis methods that are consistent with the ASME and ISO GD&T (geometric dimensioning and tolerancing) standards is a challenging task. Such methods are the basis for creating computer-aided tools for 3D tolerance analysis and assemblability analysis. These tools, along with the others, make it possible to realize virtual manufacturing, in order to shorten lead-time and reduce cost in the product development process. Current simulation tools for 3D tolerance analysis and assemblability analysis are far from satisfactory because the underlying variation algorithms are not fully consistent with the GD&T standards. Better algorithms are still to be developed. Towards that goal, this paper proposes a complete algorithm for 3D slot features and tab features (frequently used in mechanical products) for 3D simulation-based tolerance analysis. The algorithms developed account for bonus/shift tolerances (i.e. effects from material condition specifications), and tolerance zone interaction when multiple tolerances are specified on the same feature. A case study is conducted to demonstrate the algorithm developed. The result from this work is compared with that from 1D tolerance chart method. The comparison study shows quantitatively why 1D tolerance chart method, which is popular in industry, is not sufficient for tolerance analysis, which is 3D in nature.


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