Simulation-based Analysis of Ultra Thin-body Double Gate Ferroelectric TFET for an Enhanced Electric Performance

2021 ◽  
Author(s):  
GIRDHAR GOPAL ◽  
Tarun varma
Keyword(s):  
Layer Thickness ◽  
Surface Potential ◽  
Interfacial Layer ◽  
Superior Performance ◽  
Electrical Performance ◽  
Double Gate ◽  
Ultra Low Power ◽  
Ferroelectric Layer ◽  
Simulation Based ◽  
The Impact

Abstract The Ultrathin body double gate FE layer TFET(UTB-DG-FE-TFET) is proposed and investigated in this work. Electrical performance parameters such as surface potential ψ(x), electrical field, drain current, sub-threshold swing, threshold voltage, and I on /I off ratio are further analyzed using simulation-based analysis. Integration of Si: HFO 2 ferroelectric layer on top and bottom surfaces make the structure that provides negative capacitance, higher on current, enormous surface potential, peak electric field, and improvement in SS with degradation in off Current. The suggested design is evaluated in comparison with FE-TFET and standard TFET devices. Finally, the impact of device geometry variants like ferroelectric layer thickness (t fe ), intrinsic channel thickness t si , interfacial layer types, interfacial layer thickness (t ox ) and channel length L c on transfer characteristics are investigated through 2D TCAD Sentaurus Simulator for a clear validation of its optimization. The recommended work demonstrates that it is a suitable device enabling superior performance and helpful in ultra-low-power applications.

scholarly journals Geometric and process design of ultra-thin junctionless double gate vertical MOSFETs

2019 ◽  
Vol 9 (4) ◽  
pp. 2863
Author(s):  
K. E. Kaharudin ◽  
F. Salehuddin ◽  
A. S. M. Zain ◽  
Ameer F. Roslan
Keyword(s):  
Process Design ◽  
Concentration Level ◽  
Drain Current ◽  
Channel Length ◽  
Electrical Performance ◽  
Double Gate ◽  
Electrical Characteristics ◽  
Metal Gate ◽  
The Impact ◽  
Gate Work Function

The junctionless MOSFET architectures appear to be attractive in realizing the Moore’s law prediction. In this paper, a comprehensive 2-D simulation on junctionless vertical double-gate MOSFET (JLDGVM) under geometric and process consideration was introduced in order to obtain excellent electrical characteristics. Geometrical designs such as channel length (Lch) and pillar thickness (Tp) were considered and the impact on the electrical performance was analyzed. The influence of doping concentration and metal gate work function (WF) were further investigated for achieving better performance. The results show that the shorter Lch can boost the drain current (ID) of n-JLDGVM and p-JLDGVM by approximately 68% and 70% respectively. The ID of the n-JLVDGM and p-JLVDGM could possibly boost up to 42% and 78% respectively as the Tp is scaled down from 11nm to 8nm. The channel doping (Nch) is also a critical parameter, affecting the electrical performance of both n-JLDGVM and p-JLDGVM in which 15% and 39% improvements are observed in their respective ID as the concentration level is increased from 1E18 to 9E18 atom/cm3. In addition, the adjustment of threshold voltage can be realized by varying the metal WF.

scholarly journals Assessment of Interface Trap Charges on Proposed TFET for Low Power High-frequency Application

2021 ◽  
Author(s):  
Sachin Kumar ◽  
Dharmendra Singh Yadav
Keyword(s):  
Low Power ◽  
High Frequency ◽  
Superior Performance ◽  
Interface Trap ◽  
Performance Parameters ◽  
Metal Gate ◽  
Ultra Low Power ◽  
Dual Metal ◽  
The Impact ◽  
Trap Charges

Abstract Accumulation of trap charges at the semiconductor and oxide interface is the most dominating factor and cannot be neglected as it degrades device performance and reliability. This manuscript, presents detailed investigation to analyze the impact of interface trap charges (ITCs) on the performance parameters of the proposed device i.e., heterogeneous dielectric dual metal gate step channel TFET (HD DMG SC-TFET). The comparative study is conducted with dual metal gate step channel TEFT (DMG SC-TFET). The proposed device shows improved current carrying capability, suppressed ambipolar behaviour with steeper subthreshold swing. The purpose of this study to determine the ITCs impact on DC characteristics and analog/RF electrical performance parameters of the proposed device. It further observed that the proposed device exhibit superior performance due to dielectric engineering at oxide layer. Moreover, advanced communication devices must respond linearly therefore, the impact of ITCs on linearity parameters is also studied. From this brief comparative investigation, it is observed that the proposed TFET exhibits negligible distortion in linearity parameters with little or no impact of trap charges as compared to DMG SC-TFET. Thus, proposed TFET is appropriate for ultra-low power high-frequency electronic devices.

An Analytical Modeling and Performance Analysis of Graded Work Function Gate Recessed Channel SOI-MOSFET

2019 ◽  
Vol 9 (4) ◽  
pp. 504-511
Author(s):  
Sikha Mishra ◽  
Urmila Bhanja ◽  
Guru Prasad Mishra
Keyword(s):  
Analytical Model ◽  
Surface Potential ◽  
Threshold Voltage ◽  
Silicon On Insulator ◽  
Junction Depth ◽  
Short Channel ◽  
Soi Mosfet ◽  
Minimum Surface ◽  
Recessed Channel ◽  
The Impact

Introduction: A new analytical model is designed for Workfunction Modulated Rectangular Recessed Channel-Silicon On Insulator (WMRRC-SOI) MOSFET that considers the concept of groove gate and implements an idea of workfunction engineering. Methods: The impact of Negative Junction Depth (NJD) and oxide thickness (tox) are analyzed on device performances such as Sub-threshold Slope (SS), Drain Induced Barrier Lowering (DIBL) and threshold voltage. Results: The results of the proposed work are evaluated with the Rectangular Recessed Channel-Silicon On Insulator (RRC-SOI) MOSFET keeping the metal workfunction constant throughout the gate region. Furthermore, an analytical model is developed using 2D Poisson’s equation and threshold voltage is estimated in terms of minimum surface potential. Conclusion: In this work, the impact of Negative Junction Depth (NJD) on minimum surface potential and the drain current are also evaluated. It is observed from the analysis that the analog switching performance of WMRRC-SOI MOSFET surpasses RRC-SOI MOSFET in terms of better driving capability, high Ion/Ioff ratio, minimized Short Channel Effects (SCEs) and hot carrier immunity. Results are simulated using 2D Sentaurus TCAD simulator for validation of the proposed structure.

scholarly journals The Impact of Longer Consultation Time: A Simulation-Based Approach

2020 ◽  
Vol 11 (05) ◽  
pp. 857-864
Author(s):  
Abdulrahman M. Jabour
Keyword(s):  
Waiting Time ◽  
Quality Care ◽  
Working Hours ◽  
Discrete Events ◽  
Simulation Based ◽  
Patient Waiting Time ◽  
Free Environment ◽  
The Impact ◽  
Consultation Time ◽  
Patient Waiting

Abstract Background Maintaining a sufficient consultation length in primary health care (PHC) is a fundamental part of providing quality care that results in patient safety and satisfaction. Many facilities have limited capacity and increasing consultation time could result in a longer waiting time for patients and longer working hours for physicians. The use of simulation can be practical for quantifying the impact of workflow scenarios and guide the decision-making. Objective To examine the impact of increasing consultation time on patient waiting time and physician working hours. Methods Using discrete events simulation, we modeled the existing workflow and tested five different scenarios with a longer consultation time. In each scenario, we examined the impact of consultation time on patient waiting time, physician hours, and rate of staff utilization. Results At baseline scenarios (5-minute consultation time), the average waiting time was 9.87 minutes and gradually increased to 89.93 minutes in scenario five (10 minutes consultation time). However, the impact of increasing consultation time on patients waiting time did not impact all patients evenly where patients who arrive later tend to wait longer. Scenarios with a longer consultation time were more sensitive to the patients' order of arrival than those with a shorter consultation time. Conclusion By using simulation, we assessed the impact of increasing the consultation time in a risk-free environment. The increase in patients waiting time was somewhat gradual, and patients who arrive later in the day are more likely to wait longer than those who arrive earlier in the day. Increasing consultation time was more sensitive to the patients' order of arrival than those with a shorter consultation time.

Evaluating the impact of simulation-based education on clinical psychology students' confidence and clinical competence

2021 ◽  
pp. n/a-n/a
Author(s):  
Jade Sheen ◽  
Wendy Sutherland‐Smith ◽  
Emma Thompson ◽  
George J. Youssef ◽  
Amanda Dudley ◽  
...  
Keyword(s):  
Clinical Psychology ◽  
Clinical Competence ◽  
Psychology Students ◽  
Clinical Psychology Students ◽  
Simulation Based ◽  
The Impact
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