Abstract
Field Programmable Gate Arrays (FPGA) are integrated circuits (ICs) which can implement virtually any digital function and can be configured by a designer after manufacturing. This is beneficial when dedicated application-specific runs are not time or cost-effective; however, this flexibility comes at the cost of a substantially higher interconnect overhead. Three-dimensional (3D) integration can offer significant improvements in the FPGA architecture by stacking multiple device layers and interconnecting them in the third or vertical dimension, through a substrate, where path lengths are greatly reduced. This will allow for a higher density of devices and improvements in power consumption, signal integrity, and delay. Further, it facilities heterogeneous integration where additional functionalities can be incorporated into the same package as the FPGA, such as sensors, memories, and RF/analog or photonic chips, etc. Traditionally, devices have always been laid out in a planar format. 3D integration is an architecture wherein multiple layers of planar devices are stacked and interconnected using through silicon vias (TSVs) in the vertical direction.
This work will specifically detail the development of a processing and fabrication route for a three-dimensional asynchronous field programmable gate array (3D-AFPGA) design based on an extension of preexisting 2D-FPGA tile designs. Since thermal management of 3D-AFPGA is important, numerical simulations performed to predict the temperature distribution and avoid the maximum junction temperature. The numerical thermal modeling for predicting the equivalent thermal conductivity in every layer and three-dimensional temperature fields in the 3D-AFPGA are developed and discussed.
A Low-Power Field-Programmable Gate Array Routing Fabric