Low‐power and area efficient binary coded decimal adder design using a look up table‐based field programmable gate array

IET Circuits Devices & Systems ◽

10.1049/iet-cds.2015.0213 ◽

2016 ◽

Vol 10 (3) ◽

pp. 163-172 ◽

Author(s):

Zarrin Tasnim Sworna ◽

Mubin UlHaque ◽

Nazma Tara ◽

Hafiz Md. Hasan Babu ◽

Ashis Kumar Biswas

Keyword(s):

Low Power ◽

Field Programmable Gate Array ◽

Look Up Table ◽

Field Programmable ◽

Decimal Adder ◽

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Variation-tolerant and low power look-up table (LUT) using spin-torque transfer magnetic RAM for non-volatile field programmable gate array (FPGA)

2016 International SoC Design Conference (ISOCC) ◽

10.1109/isocc.2016.7799753 ◽

2016 ◽

Author(s):

Kangwook Jo ◽

Kyungseon Cho ◽

Hongil Yoon

Keyword(s):

Low Power ◽

Field Programmable Gate Array ◽

Spin Torque ◽

Spin Torque Transfer ◽

Look Up Table ◽

Field Programmable ◽

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Nonvolatile Configuration Memory Cell for Low Power Field Programmable Gate Array

2011 3rd IEEE International Memory Workshop (IMW) ◽

10.1109/imw.2011.5873238 ◽

2011 ◽

Author(s):

Shinichi Yasuda ◽

Kazutaka Ikegami ◽

Tetsufumi Tanamoto ◽

Atsuhiro Kinoshita ◽

Keiko Abe ◽

...

Keyword(s):

Low Power ◽

Field Programmable Gate Array ◽

Memory Cell ◽

Field Programmable ◽

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A Low-Power Field-Programmable Gate Array Routing Fabric

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2008.2005098 ◽

2009 ◽

Vol 17 (10) ◽

pp. 1481-1494 ◽

Author(s):

Mingjie Lin ◽

A. El Gamal

Keyword(s):

Low Power ◽

Field Programmable Gate Array ◽

Field Programmable ◽

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Nonvolatile field-programmable gate array using 2-transistor–1-MTJ-cell-based multi-context array for power and area efficient dynamically reconfigurable logic

Japanese Journal of Applied Physics ◽

10.7567/jjap.54.04de01 ◽

2015 ◽

Vol 54 (4S) ◽

pp. 04DE01 ◽

Author(s):

Daisuke Suzuki ◽

Takahiro Hanyu

Keyword(s):

Field Programmable Gate Array ◽

Reconfigurable Logic ◽

Dynamically Reconfigurable ◽

Field Programmable ◽

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Low power field programmable gate array implementation of fast digital signal processing algorithms: characterisation and manipulation of data locality

IET Computers & Digital Techniques ◽

10.1049/iet-cdt.2010.0052 ◽

2011 ◽

Vol 5 (2) ◽

pp. 136 ◽

Author(s):

S. McKeown ◽

R. Woods

Keyword(s):

Signal Processing ◽

Digital Signal Processing ◽

Low Power ◽

Field Programmable Gate Array ◽

Digital Signal ◽

Data Locality ◽

Field Programmable ◽

Signal Processing Algorithms ◽

Processing Algorithms ◽

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A hybrid CBRAM/CMOS Look-Up-Table structure for improving performance efficiency of Field-Programmable-Gate-Array

2013 IEEE International Symposium on Circuits and Systems (ISCAS2013) ◽

10.1109/iscas.2013.6572372 ◽

2013 ◽

Author(s):

Santhosh Onkaraiah ◽

Ogun Turkyilmaz ◽

Marina Reyboz ◽

Fabien Clermidy ◽

Elisa Vianello ◽

...

Keyword(s):

Field Programmable Gate Array ◽

Look Up Table ◽

Field Programmable ◽

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Optimization Design of Low Power Consumption Kalman Filter Based on Field Programmable Gate Array

Journal of Nanoelectronics and Optoelectronics ◽

10.1166/jno.2016.1998 ◽

2016 ◽

Vol 11 (6) ◽

pp. 677-684 ◽

Author(s):

Lv Changzhi ◽

Li Weikuo ◽

Song Jun ◽

Fan Di ◽

Lu Xiushan

Keyword(s):

Kalman Filter ◽

Power Consumption ◽

Low Power ◽

Field Programmable Gate Array ◽

Optimization Design ◽

Low Power Consumption ◽

Field Programmable ◽

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Low-Power, Low-Latency Hermite Polynomial Characterization of Heartbeats Using a Field-Programmable Gate Array

Bioinformatics and Biomedical Engineering - Lecture Notes in Computer Science ◽

10.1007/978-3-319-31744-1_24 ◽

2016 ◽

pp. 266-276 ◽

Author(s):

Kartik Lakhotia ◽

Gabriel Caffarena ◽

Alberto Gil ◽

David G. Márquez ◽

Abraham Otero ◽

...

Keyword(s):

Low Power ◽

Field Programmable Gate Array ◽

Hermite Polynomial ◽

Low Latency ◽

Field Programmable ◽

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Different Configuration of Low-Power Memory Design Using Capacitance Scaling on 28-nm Field-Programmable Gate Array

System and Architecture - Advances in Intelligent Systems and Computing ◽

10.1007/978-981-10-8533-8_15 ◽

2018 ◽

pp. 151-161 ◽

Author(s):

Inderpreet Kaur ◽

Lakshay Rohilla ◽

Alisha Nagpal ◽

Bishwajeet Pandey ◽

Sanchit Sharma

Keyword(s):

Low Power ◽

Field Programmable Gate Array ◽

Memory Design ◽

Field Programmable ◽

Capacitance Scaling ◽

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Low-Power CMOS/Nanomaterial Three-Dimensional Field Programmable Gate Array Architecture

Quantum Matter ◽

10.1166/qm.2016.1351 ◽

2016 ◽

Vol 5 (4) ◽

pp. 612-615

Author(s):

Hojjat Sharifi ◽

Fazel Sharifi ◽

Armin Belghadr

Keyword(s):

Low Power ◽

Field Programmable Gate Array ◽

Three Dimensional ◽

Array Architecture ◽

Field Programmable ◽

Low Power Cmos ◽

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