Decimal Multiplication in FPGA with a Novel Decimal Adder/Subtractor

Financial and commercial data are mostly represented in decimal format. To avoid errors introduced when converting some decimal fractions to binary, these data are processed with decimal arithmetic. Most processors only have hardwired binary arithmetic units. So, decimal operations are executed with slow software-based decimal arithmetic functions. For the fast execution of decimal operations, dedicated hardware units have been proposed and designed in FPGA. Decimal multiplication is found in most decimal-based applications and so its optimized design is very important for fast execution. In this paper two new parallel decimal multipliers in FPGA are proposed. These are based on a new decimal adder/subtractor also proposed in this paper. The new decimal multipliers improve state-of-the-art parallel decimal multipliers. Compared to previous architectures, implementation results show that the proposed multipliers achieve 26% better area and 12% better performance. Also, the new decimal multipliers reduce the area and performance gap to binary multipliers and are smaller for 32 digit operands.

On The Implementation of Densely Packed Decimal Number System Based Adder: Prospects and Challenges

Decimal digit number computation, through bit compression methodology, offers space and time saving, which can be incurred by the Chen-Ho and Densely Packed Decimal (DPD) coding techniques. Such coding techniques have a property of bit compression, like, three decimal digits can be represented by 10 bits instead of 12 bits in binary coded decimal (BCD) format. The compression has been obtained through the elimination of the redundant 0’s from BCD representation. This manuscript reports the pros and cons of the techniques mentioned above. The logic level functionalities have been examined through MATLAB, whereas circuit simulation has been erified through Cadence Spectre. Performance parameters (such as delay, power consumption) have been evaluated through CMOS gpdk45 nm technology. Furthermore, the best design has been chosen from them, and the decimal adder design technique has been incorporated in this paper.

A Low Quantum Cost Implementation of Reversible Binary-Coded-Decimal Adder

The prediction and forthcoming of a quantum computer into the real-world is the much gained research area over the last decades, which initiated the usefulness and profit of reversible computation because of its potentiality to reduce power consumption in designing arithmetic circuits. In this paper, two design approaches are proposed for the design of a reversible Binary-Coded-Decimal adder. The first approach is implemented and realized from reversible gates proposed by researchers in the technical literature capable of breaking down into primitive quantum gates, whereas the second approach is realized from the existing synthesizable reversible gates only. Parallel implementations of such circuits have been carried out through the proper selection and arrangements of the gates to improve the reversible performance parameters. The proposed design approaches offer a low quantum cost along-with lower delay and hardware complexity for any n-digit addition. Analysis results of proposed design 1 show appreciable improvements over gate count, quantum cost, and delay by at least 9 %, 17 %, and 26 % respectively, whereas, the proposed design 2 show that the results significantly improve the parameters (gate count, quantum cost, and delay) by at least 45 %, 33 %, and 50 % respectively compared to existing counterparts found in the literature.

Design and Implementation of Reduced Power Energy Efficient Binary Coded Decimal Adder

<p>This paper presents a novel architecture for low power energy binary represented decimal addition. The proposed BCD adder uses Binary to Excess Six Converter (BESC) block for constant correction to adjusts binary outputs exceeding 9 to correct decimal values and exploits the inherent advantage of reduced delay and switching, due to elimination of long carry propagation in second stage addition as in conventional design and switching OFF of the BESC block for decimal outputs less than 9. The proposed BESC-BCD adder has been designed using VHDL code and synthesized using Altera Quartus II. Experimental results demonstrates that the proposed decimal adder can lead to significant power savings and delay reduction compared to existing BCD adders which is realised in better power-delay product(PDP) performance. For example the PDP saving of the proposed BESC-BCD adder for a 1 digit and 2 digit addition implementations are 11.6% and 16.05% respectively, compared to the best of the designs used for comparison.</p>