A medium-scale hybrid interface

SIMULATION ◽  
1968 ◽  
Vol 10 (5) ◽  
pp. 225-233 ◽  
Author(s):  
G.P. Marston ◽  
J.S. MacDonald
Keyword(s):  
Digital Computer ◽  
High Speed ◽  
Data Transfer ◽  
Low Cost ◽  
Analog Computer ◽  
Digital Data ◽  
Analog To Digital ◽  
Medium Scale ◽  
Signal Selection ◽  
Hybrid Interface

A flexible, low-cost hybrid interface linking a DEC PDP-9 digital computer with an EAI 231 R-V analog computer is described. The interface includes provision for complete mode control of the 231 R-V by the PDP-9, as well as signal selection and potentiometer setting facilities. Data transfer is accomplished by using double-buffered D/A registers with provision for controlling the transfer of data from either the analog or digital side of the interface. In addi tion, provision is made for the updating of several D/A channels simultaneously. A sixteen channel analog multi plexer with a settling-time of less than two microseconds has been designed and is employed with a twelve-bit twenty-microsecond A/D converter for high-speed analog- to-digital data transfer.

Detecting Malicious Switches for a Secure Software-defined Tactile Internet

2021 ◽  
Vol 21 (4) ◽  
pp. 1-23
Author(s):  
Bin Yuan ◽  
Chen Lin ◽  
Deqing Zou ◽  
Laurence Tianruo Yang ◽  
Hai Jin
Keyword(s):  
High Speed ◽  
Data Transfer ◽  
Low Cost ◽  
Rapid Development ◽  
Denial Of Service ◽  
Linear Structure ◽  
Network Layers ◽  
High Speed Data ◽  
Network Status ◽  
Sdn Controller

The rapid development of the Internet of Things has led to demand for high-speed data transformation. Serving this purpose is the Tactile Internet, which facilitates data transfer in extra-low latency. In particular, a Tactile Internet based on software-defined networking (SDN) has been broadly deployed because of the proven benefits of SDN in flexible and programmable network management. However, the vulnerabilities of SDN also threaten the security of the Tactile Internet. Specifically, an SDN controller relies on the network status (provided by the underlying switches) to make network decisions, e.g., calculating a routing path to deliver data in the Tactile Internet. Hence, the attackers can compromise the switches to jeopardize the SDN and further attack Tactile Internet systems. For example, an attacker can compromise switches to launch distributed denial-of-service attacks to overwhelm the SDN controller, which will disrupt all the applications in the Tactile Internet. In pursuit of a more secure Tactile Internet, the problem of abnormal SDN switches in the Tactile Internet is analyzed in this article, including the cause of abnormal switches and their influences on different network layers. Then we propose an approach that leverages the messages sent by all switches to identify abnormal switches, which adopts a linear structure to store historical messages at a relatively low cost. By mapping each flow message to the flow establishment model, our method can effectively identify malicious SDN switches in the Tactile Internet and thus enhance its security.

Low Noise EEG Amplifier Board for Low Cost Wearable BCI Devices

2016 ◽  
Vol 5 (2) ◽  
pp. 17-28
Author(s):  
Ravim ◽  
Suma K. V.
Keyword(s):  
Noise Reduction ◽  
Digital Signal Processor ◽  
Low Cost ◽  
Processing System ◽  
Digital Signal ◽  
Low Noise ◽  
Digital Data ◽  
Signal Processing System ◽  
Analog To Digital ◽  
Reduction Techniques

Designing a real-time BCI device requires an Electroencephalogram (EEG) acquisition system and a signal processing system to process that acquired data. EEG acquisition boards available in market are expensive and they are required to be connected to computer for any processing work. Various low cost Digital Signal Processor (DSP) boards available in market come with internal Analog to Digital converters and peripheral interfaces. The idea is to design a low cost EEG amplifier board that can be used with these commercially available DSP boards. The analog data from EEG amplifier can be converted to digital data by DSP board and sent to computer via an interface for algorithm development and further control operations. EEG amplifiers are highly affected by noise from environment. Proper noise reduction techniques are implemented and simulated in circuit design. Each filter stage and noise reduction circuit is evaluated for a low noise design.

A technique for high-speed digital data transfer based on crosstalk

2006 ◽  
Vol 89 (12) ◽  
pp. 43-52
Author(s):  
Hideki Osaka ◽  
Yukata Uematsu ◽  
Yasunori Sakisaka ◽  
Hiroaki Ikeda
Keyword(s):  
High Speed ◽  
Data Transfer ◽  
Digital Data

The DES-1A New Digital Computer for Solving Differential Equations

SIMULATION ◽  
1965 ◽  
Vol 4 (4) ◽  
pp. 264-276 ◽  
Author(s):  
Leon Levine
Keyword(s):  
Differential Equations ◽  
Data Storage ◽  
Digital Computer ◽  
High Speed ◽  
Initial Conditions ◽  
Analog Computer ◽  
Rapid Communication ◽  
Floating Point Arithmetic ◽  
Point Arithmetic ◽  
Computer Operator

The DES-1 is a new digital computer system, espe cially designed for the solution of ordinary differ ential equations. The major components are (1) the SDS 9300, a high-speed digital computer, ( 2) a mathe matical operator language, and (3) a console. The mathematical operator language is analogous to the computing elements of the analog computer. Thus both the DES-1 and analog computer can be programmed the same way (although the DES-1 has several more operations). Consequently an analog computer operator can learn to program the DES-1 easily and can use much of the programming expe rience acquired on the analog computer. Further more, the use of floating-point arithmetic eliminates all need for amplitude scaling. The console provides rapid communication between the operator and the DES-1 and allows problem mode control and changes even as the com putations are being made. Some of the modes are RESET, OPERATE, and HOLD, while typical changes include parameters, initial conditions, and even equa tion structure. The DES-1, therefore, combines the advantages of the digital computer 1. Accuracy 2. Reliability 3. Ease of program and data storage 4. Ability to perform algebraic operations with those of the analog computer 1. Convenience of programming through use of the mathematical operator language 2. Rapid communication between operator and computer to produce a computer which has advantages over both conventional analog and digital computers in solving differential equations.

scholarly journals Modeling-Based Design of Memristive Devices for Brain-Inspired Computing

2021 ◽  
Vol 3 ◽  
Author(s):  
Yudi Zhao ◽  
Ruiqi Chen ◽  
Peng Huang ◽  
Jinfeng Kang
Keyword(s):  
Resistive Switching ◽  
High Speed ◽  
Data Transfer ◽  
Low Cost ◽  
Random Access ◽  
Processing Unit ◽  
Computing Systems ◽  
Stochastic Computing ◽  
Non Volatile Memory ◽  
Physical Effects

Resistive switching random access memory (RRAM) has emerged for non-volatile memory application with the features of simple structure, low cost, high density, high speed, low power, and CMOS compatibility. In recent years, RRAM technology has made significant progress in brain-inspired computing paradigms by exploiting its unique physical characteristics, which attempts to eliminate the energy-intensive and time-consuming data transfer between the processing unit and the memory unit. The design of RRAM-based computing paradigms, however, requires a detailed description of the dominant physical effects correlated with the resistive switching processes to realize the interaction and optimization between devices and algorithms or architectures. This work provides an overview of the current progress on device-level resistive switching behaviors with detailed insights into the physical effects in the resistive switching layer and the multifunctional assistant layer. Then the circuit-level physics-based compact models will be reviewed in terms of typical binary RRAM and the emerging analog synaptic RRAM, which act as an interface between the device and circuit design. After that, the interaction between device and system performances will finally be addressed by reviewing the specific applications of brain-inspired computing systems including neuromorphic computing, in-memory logic, and stochastic computing.

scholarly journals Interrupt Enabled Priority Based Master Slave Communication using SPI Protocol

2020 ◽  
Vol 9 (9) ◽  
pp. 564-567
Keyword(s):  
Data Transfer ◽  
Low Cost ◽  
Full Duplex ◽  
Control Block ◽  
Digital To Analog Converter ◽  
Analog To Digital ◽  
High Speeds ◽  
Analog Converter ◽  
Serial Peripheral Interface ◽  
Very High

Serial Peripheral Interface or SPI is a synchronous serial communication protocol that provides full – duplex communication at very high speeds. It is a master – slave type protocol that provides a simple and low-cost interface between a microcontroller and its peripherals. This paper proposes the design of a priority-based master slave communication system using SPI Protocol that enables the system to operate using interrupts. The design mainly emphasizes on priority-based communication where the slaves will generate an interrupt over a newly defined interrupt pin when some data transfer needs to happen. When the master receives an interrupt from the slave it establishes communication with one slave at a time based on the priority and the priority to each slave is assigned by the arbiter or priority control block. The highest priority slave is served first. Shift register is used to store and transfer the data bit by bit and it resets every time a data transfer is complete. The design proposed here can be implemented in different applications which involve the peripherals that can support SPI protocol for communication such as LCDs, Analog to Digital Converter, Digital to Analog Converter, Memory Cards, Temperature Sensor, Pressure Sensor. In this work, a single master multi slave architecture is considered. The design given in this paper can be scaled up to support more than four slaves.

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