The DES-1A New Digital Computer for Solving Differential Equations

SIMULATION ◽  
1965 ◽  
Vol 4 (4) ◽  
pp. 264-276 ◽  
Author(s):  
Leon Levine
Keyword(s):  
Differential Equations ◽  
Data Storage ◽  
Digital Computer ◽  
High Speed ◽  
Initial Conditions ◽  
Analog Computer ◽  
Rapid Communication ◽  
Floating Point Arithmetic ◽  
Point Arithmetic ◽  
Computer Operator

The DES-1 is a new digital computer system, espe cially designed for the solution of ordinary differ ential equations. The major components are (1) the SDS 9300, a high-speed digital computer, ( 2) a mathe matical operator language, and (3) a console. The mathematical operator language is analogous to the computing elements of the analog computer. Thus both the DES-1 and analog computer can be programmed the same way (although the DES-1 has several more operations). Consequently an analog computer operator can learn to program the DES-1 easily and can use much of the programming expe rience acquired on the analog computer. Further more, the use of floating-point arithmetic eliminates all need for amplitude scaling. The console provides rapid communication between the operator and the DES-1 and allows problem mode control and changes even as the com putations are being made. Some of the modes are RESET, OPERATE, and HOLD, while typical changes include parameters, initial conditions, and even equa tion structure. The DES-1, therefore, combines the advantages of the digital computer 1. Accuracy 2. Reliability 3. Ease of program and data storage 4. Ability to perform algebraic operations with those of the analog computer 1. Convenience of programming through use of the mathematical operator language 2. Rapid communication between operator and computer to produce a computer which has advantages over both conventional analog and digital computers in solving differential equations.

scholarly journals The Frequency Response of Glaciers

1965 ◽  
Vol 5 (41) ◽  
pp. 567-587 ◽  
Author(s):  
J. F. Nye
Keyword(s):  
Differential Equations ◽  
Frequency Response ◽  
Digital Computer ◽  
High Speed ◽  
Computer Programme ◽  
Fixed Frequency ◽  
Response Curves ◽  
Double Peak ◽  
Low Frequencies ◽  
Rate Of Accumulation

AbstractThe theory developed in previous papers to represent the response of a glacier to changes in the rate of accumulation and ablation has been used for a number of applications. A method of integrating the differential equations for a fixed frequency was programmed for a high-speed digital computer. This provides a better way of finding the frequency response than the earlier method which used series approximations or high and low frequencies. Results are given for (a) an artificial glacier showing varying amounts of diffusion of the kinematic waves, (b) South Cascade Glacier, Washington, U.S.A., as a check on previous results, and (c) Storglaciären, Kebrekaise, Sweden. The response curves of Storglaciären are very similar in shape In those of South Cascade Glacier but, since. Storglaciären moves more slowly, the curves are shifted in frequency (by a factor of two). The phase of the response at the terminus of Storglaciären plotted against frequency shows a double peak.Certain mathematical results for the artificial case of no diffusion are given in an Appendix.A computer programme was also written for calculatingλandμcoefficients and applied to South Cascade Glacier and Storglaciären.

Implementation of Embedded Floating Point Arithmetic Units on FPGA

2014 ◽  
Vol 550 ◽  
pp. 126-136
Author(s):  
N. Ramya Rani
Keyword(s):  
High Speed ◽  
High Performance ◽  
Floating Point ◽  
Double Precision ◽  
Embedded Computing ◽  
Floating Point Arithmetic ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Arithmetic Units ◽  
Point Arithmetic

:Floating point arithmetic plays a major role in scientific and embedded computing applications. But the performance of field programmable gate arrays (FPGAs) used for floating point applications is poor due to the complexity of floating point arithmetic. The implementation of floating point units on FPGAs consumes a large amount of resources and that leads to the development of embedded floating point units in FPGAs. Embedded applications like multimedia, communication and DSP algorithms use floating point arithmetic in processing graphics, Fourier transformation, coding, etc. In this paper, methodologies are presented for the implementation of embedded floating point units on FPGA. The work is focused with the aim of achieving high speed of computations and to reduce the power for evaluating expressions. An application that demands high performance floating point computation can achieve better speed and density by incorporating embedded floating point units. Additionally this paper describes a comparative study of the design of single precision and double precision pipelined floating point arithmetic units for evaluating expressions. The modules are designed using VHDL simulation in Xilinx software and implemented on VIRTEX and SPARTAN FPGAs.

A Novel FPGA based Leading One Anticipation Algorithm for Floating Point Arithmetic Units

2012 ◽  
Vol 1 (1) ◽  
pp. 19
Author(s):  
Ashwini Suresh Deshmukh
Keyword(s):  
High Speed ◽  
State Of The Art ◽  
Multimedia Systems ◽  
Floating Point ◽  
Silicon Area ◽  
Latency Reduction ◽  
Floating Point Arithmetic ◽  
Total Latency ◽  
Arithmetic Units ◽  
Point Arithmetic

In multimedia Systems-on-Chips, the design of specialized IEEE-754-compliant floating point arithmetic units (FPU) is critical with respect to both operating speed and silicon area demand. Leading one anticipation is a well-known issue in the implementation of high speed FPUs. We investigated a novel leading one anticipation algorithm allowing us to significantly reduce the anticipation failure rate with respect to the state-of the art. We embedded our technique into a complete FPU and compared its performance against existing solutions, definitely showing both area savings and total latency reduction.

Real-time simulation of a helicopter rotor on an analog computer

SIMULATION ◽  
1970 ◽  
Vol 14 (5) ◽  
pp. 231-237
Author(s):  
Milton Schramm
Keyword(s):  
Real Time ◽  
Hybrid Systems ◽  
High Speed ◽  
Initial Conditions ◽  
Analog Computer ◽  
Helicopter Rotor ◽  
Real Time Simulation ◽  
Time Simulation ◽  
Hybrid Computer ◽  
Lift And Drag

An accurate real-time simulation of a helicopter rotor can be achieved on a high-speed analog computer. By using repetitive operation and integrating along each blade every 2.5 milliseconds, the double integration required to determine rotor torque, thrust, moment, and rearward and sideward rotor forces is accomplished. The lift and drag coefficients are continuously calculated at all points along the blade. The same analog equipment used to calculate quantities for one blade is used for other blades by chang ing appropriate initial conditions. This analysis provides a transient rotor solution in which integration out the blade is accomplished every five rotor azimuth degrees. One console of a Hybrid Systems, Inc., SS-100 Analog/Hybrid Computer is used for the rotor solution.

scholarly journals HIGH-SPEED, AREA-EFFICIENT FPGA-BASED FLOATING-POINT ARITHMETIC MODULES

2006 ◽  
Vol 34 (4) ◽  
pp. 1283-1292
Author(s):  
M. Taher ◽  
M. Aboulwafa ◽  
A. Abdelwahab ◽  
E. M. Saad
Keyword(s):  
High Speed ◽  
Floating Point ◽  
Floating Point Arithmetic ◽  
Point Arithmetic ◽  
Area Efficient
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