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Global Interconnect Planning
Handbook of Algorithms for Physical Design Automation
◽
10.1201/9781420013481.ch33
◽
2008
◽
Author(s):
Cheng-Kok Koh
◽
Evangeline Young
◽
Yao-Wen Chang
Keyword(s):
Global Interconnect
◽
Interconnect Planning
Download Full-text
Related Documents
Cited By
References
Global Interconnect Planning
Handbook of Algorithms for Physical Design Automation
◽
10.1201/9781420013481-33
◽
2008
◽
pp. 645-672
Author(s):
Cheng-Kok Koh
◽
Evangeline F.Y. Young
◽
Yao-Wen Chang
Keyword(s):
Global Interconnect
◽
Interconnect Planning
Download Full-text
Exploration of Segmented Bus As Scalable Global Interconnect for Neuromorphic Computing
Proceedings of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI '19
◽
10.1145/3299874.3319491
◽
2019
◽
Cited By ~ 2
Author(s):
Adarsha Balaji
◽
Yuefeng Wu
◽
Anup Das
◽
Francky Catthoor
◽
Siebren Schaafsma
Keyword(s):
Neuromorphic Computing
◽
Global Interconnect
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A global interconnect link design for many-core microprocessors
Proceedings of the 1st international forum on Next-generation multicore/manycore technologies - IFMT '08
◽
10.1145/1463768.1463787
◽
2008
◽
Cited By ~ 1
Author(s):
DiaaEldin Khalil
◽
Yehea Ismail
Keyword(s):
Global Interconnect
◽
Many Core
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Design optimization for AC coupled on-chip global interconnect
2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)
◽
10.1109/icsict.2016.7998789
◽
2016
◽
Author(s):
Jianfei Jiang
◽
Qin Wang
◽
Weifeng He
◽
Xiaoyang Zeng
Keyword(s):
Design Optimization
◽
Global Interconnect
◽
On Chip
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A New Global Interconnect Paradigm: MIM Power-Ground Plane Capacitors
2006 International Interconnect Technology Conference
◽
10.1109/iitc.2006.1648643
◽
2006
◽
Author(s):
D.C. Sekar
◽
E. Demaray
◽
Hongmei Zhang
◽
P.A. Kohl
◽
J.D. Meindl
Keyword(s):
Ground Plane
◽
Global Interconnect
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An explicit and unconditionally stable time-domain finite-element method of linear complexity for electromagnetics-based simulation of 3-D global interconnect network
2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems
◽
10.1109/epeps.2011.6100222
◽
2011
◽
Cited By ~ 5
Author(s):
Qing He
◽
Duo Chen
◽
Dan Jiao
Keyword(s):
Finite Element Method
◽
Finite Element
◽
Time Domain
◽
Linear Complexity
◽
Unconditionally Stable
◽
Global Interconnect
◽
Interconnect Network
◽
Element Method
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Interconnect planning with local area constrained retiming [logic IC layout]
2003 Design, Automation and Test in Europe Conference and Exhibition
◽
10.1109/date.2003.1253649
◽
2003
◽
Author(s):
Ruibing Lu
◽
Cheng-Kok Koh
Keyword(s):
Local Area
◽
Interconnect Planning
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Air-Gap Technology With a Large Void-Fraction for Global Interconnect Delay Reduction
IEEE Transactions on Electron Devices
◽
10.1109/ted.2021.3105086
◽
2021
◽
pp. 1-7
Author(s):
Clarissa Prawoto
◽
Zichao Ma
◽
Ying Xiao
◽
Salahuddin Raju
◽
Mansun Chan
Keyword(s):
Void Fraction
◽
Air Gap
◽
Delay Reduction
◽
Large Void
◽
Interconnect Delay
◽
Global Interconnect
◽
Gap Technology
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Design optimization for capacitive-resistively driven on-chip global interconnect
IEICE Electronics Express
◽
10.1587/elex.12.20150111
◽
2015
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Vol 12
(8)
◽
pp. 20150111-20150111
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Cited By ~ 1
Author(s):
Jianfei Jiang
◽
Weifeng He
◽
Jizeng Wei
◽
Qin Wang
◽
Zhigang Mao
Keyword(s):
Design Optimization
◽
Global Interconnect
◽
On Chip
Download Full-text
Self-Timed Regenerators for High-Speed and Low-Power On-Chip Global Interconnect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
◽
10.1109/tvlsi.2008.2000250
◽
2008
◽
Vol 16
(6)
◽
pp. 673-677
◽
Cited By ~ 3
Author(s):
Prashant Singh
◽
Jae-sun Seo
◽
David Blaauw
◽
Dennis Sylvester
Keyword(s):
Low Power
◽
High Speed
◽
Global Interconnect
◽
On Chip
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