A Vernier Delay Line for Time Interval Measurement
2011 ◽
Vol 301-303
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pp. 995-1000
Keyword(s):
This paper presents a Vernier Delay Line (VDL) for time interval measurement. A dedicated multiplexer is inserted into each stage of the proposed VDL. As a result, the D-flip-flops in each stage can be served as a large delay cell as well as a traditional arbiter. Moreover, the proposed interface circuit can save time residue out for further fine granularity measurement. Experimental results show that the proposed VDL achieves a 30ns measurement range with 6600 transistors.
Keyword(s):
2014 ◽
Vol 21
(1)
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pp. 77-84
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Keyword(s):
2016 ◽
Vol 62
(3)
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pp. 237-246
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2008 ◽
Vol 57
(6)
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pp. 1244-1250
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