HIGH RESOLUTION TIME-INTERVAL MEASUREMENT SYSTEMS APPLIED TO FLOW MEASUREMENT

2014 ◽  
Vol 21 (1) ◽  
pp. 77-84 ◽  
Author(s):  
Sławomir Grzelak ◽  
Marcin Kowalski ◽  
Jarosław Czoków ◽  
Marek Zieliński
Keyword(s):  
High Resolution ◽  
Flow Measurement ◽  
Delay Line ◽  
Time Interval ◽  
Clock Signal ◽  
Resolution Time ◽  
Interval Measurement ◽  
Measurement Systems ◽  
Field Programmable ◽  
Time Interval Measurement

Abstract The designing process of high resolution time interval measurement systems creates many problems that need to be eliminated. The problems are: the latch error, the nonlinearity conversion, the different duty cycle coefficient of the clock signal, and the clock signal jitter. Factors listed above affect the result of measurement. The FPGA (Field Programmable Gate Array) structure also imposes some restrictions, especially when a tapped delay line is constructed. The article describes the high resolution time-to-digital converter, implemented in a FPGA structure, and the types of errors that appear there. The method of minimization and processing of data to reduce the influence of errors on the measurement is also described.

scholarly journals Architecture of the multi-tap-delay-line time-interval measurement module implemented in FPGA device

ACTA IMEKO ◽  
2015 ◽  
Vol 4 (1) ◽  
pp. 77
Author(s):  
Marek Zielinski ◽  
Maciej Gurski ◽  
Dariusz Chaberski
Keyword(s):  
High Resolution ◽  
Duty Cycle ◽  
Delay Line ◽  
Measurement Instrument ◽  
Time Interval ◽  
Interval Measurement ◽  
Time Stamps ◽  
Measured Time ◽  
Time Interval Measurement ◽  
Total Measurement Time

This paper describes the architecture of a Multi-Tap-Delay-Line (MTDL) time-interval measurement module of high resolution implemented in a single FPGA device. The new architecture of the measurement module enables to collect sixteen time-stamps during a single measuring cycle. It means that the measured time-interval can be precisely interpolated from the collection of the sixteen time-stamps after each measuring cycle. Such architecture of the measurement module leads directly to an increased resolution, to a limited total measurement time and a decreased duty cycle of the measurement instrument.

A high-resolution digital time-interval measurement instrument

Measurement ◽  
1997 ◽  
Vol 22 (3-4) ◽  
pp. 129-140 ◽  
Author(s):  
Domenico Mirri ◽  
Gaetano Pasini ◽  
Gaetano Iuculano ◽  
Fabio Filicori ◽  
Gabriella Pellegrini ◽  
...  
Keyword(s):  
High Resolution ◽  
Measurement Instrument ◽  
Time Interval ◽  
Interval Measurement ◽  
Time Interval Measurement ◽  
Digital Time

Ultrasonic Flow Measurement with High Resolution

2014 ◽  
Vol 21 (2) ◽  
pp. 305-316 ◽  
Author(s):  
Sławomir Grzelak ◽  
Jarosław Czoków ◽  
Marcin Kowalski ◽  
Marek Zieliński
Keyword(s):  
High Resolution ◽  
Wave Packet ◽  
Ultrasonic Transducer ◽  
Ultrasonic Pulse ◽  
Ultrasonic Flowmeter ◽  
Time Interval ◽  
Interval Measurement ◽  
Characteristic Wave ◽  
Time Stamps ◽  
Time Interval Measurement

Abstract The ultrasonic flowmeter which is described in this paper, measures the transit of time of an ultrasonic pulse. This device consists of two ultrasonic transducers and a high resolution time interval measurement module. An ultrasonic transducer emits a characteristic wave packet (transmit mode). When the transducer is in receive mode, a characteristic wave packet is formed and it is connected to the time interval measurement module inputs. The time interval measurement module allows registration of transit time differences of a few pulses in the packet. In practice, during a single measuring cycle a few time-stamps are registered. Moreover, the measurement process is also synchronous and, by applying the statistics, the time interval measurement uncertainty improves even in a single measurement. In this article, besides a detailed discussion on the principle of operation of the ultrasonic flowmeter implemented in the FPGA structure, also the test results are presented and discussed

A Vernier Delay Line for Time Interval Measurement

2011 ◽  
Vol 301-303 ◽  
pp. 995-1000
Author(s):  
Xin Gang Wang ◽  
Fei Wang ◽  
Hai Gang Yang
Keyword(s):  
Delay Line ◽  
Measurement Range ◽  
Experimental Results ◽  
Time Interval ◽  
Large Delay ◽  
Interval Measurement ◽  
Interface Circuit ◽  
Delay Cell ◽  
Time Interval Measurement

This paper presents a Vernier Delay Line (VDL) for time interval measurement. A dedicated multiplexer is inserted into each stage of the proposed VDL. As a result, the D-flip-flops in each stage can be served as a large delay cell as well as a traditional arbiter. Moreover, the proposed interface circuit can save time residue out for further fine granularity measurement. Experimental results show that the proposed VDL achieves a 30ns measurement range with 6600 transistors.

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