Architecture of the multi-tap-delay-line time-interval measurement module implemented in FPGA device
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This paper describes the architecture of a Multi-Tap-Delay-Line (MTDL) time-interval measurement module of high resolution implemented in a single FPGA device. The new architecture of the measurement module enables to collect sixteen time-stamps during a single measuring cycle. It means that the measured time-interval can be precisely interpolated from the collection of the sixteen time-stamps after each measuring cycle. Such architecture of the measurement module leads directly to an increased resolution, to a limited total measurement time and a decreased duty cycle of the measurement instrument.
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2014 ◽
Vol 21
(2)
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pp. 305-316
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2014 ◽
Vol 21
(1)
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pp. 77-84
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2016 ◽
Vol 62
(3)
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pp. 237-246
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2011 ◽
Vol 301-303
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pp. 995-1000
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2011 ◽
Vol 56
(12)
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pp. 1285-1290
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