A Novel Two-Split Capacitor Array with Linearity Analysis for High-Resolution SAR ADCs

Author(s):  
Yingxin Zheng ◽  
Zongmin Wang ◽  
Song Yang ◽  
Qizhang Li ◽  
Li Xiang
2007 ◽  
Vol 42 (4) ◽  
pp. 739-747 ◽  
Author(s):  
Brian P. Ginsburg ◽  
Anantha P. Chandrakasan

Author(s):  
Yan Zhu ◽  
U-Fat Chio ◽  
He-Gong Wei ◽  
Sai-Weng Sin ◽  
Seng-Pan U ◽  
...  

2017 ◽  
Vol 38 (10) ◽  
pp. 105008 ◽  
Author(s):  
Chao Cao ◽  
Zhangming Zhu

VLSI Design ◽  
2010 ◽  
Vol 2010 ◽  
pp. 1-8 ◽  
Author(s):  
Yan Zhu ◽  
U-Fat Chio ◽  
He-Gong Wei ◽  
Sai-Weng Sin ◽  
Seng-Pan U ◽  
...  

A novel Capacitor array structure for Successive Approximation Register (SAR) ADC is proposed. This circuit efficiently utilizes charge recycling to achieve high-speed of operation and it can be applied to high-speed and low-to-medium-resolution SAR ADC. The parasitic effects and the static linearity performance, namely, the INL and DNL, of the proposed structure are theoretically analyzed and behavioral simulations are performed to demonstrate its effectiveness under those nonidealities. Simulation results show that to achieve the same conversion performance the proposed capacitor array structure can reduce the average power consumed from the reference ladder by 90% when compared to the binary-weighted splitting capacitor array structure.


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