scholarly journals A Motion Estimation based Algorithm for Encoding Time Reduction in HEVC

2022 ◽  
Vol 72 (1) ◽  
pp. 56-66
Author(s):  
S. Karthik Sairam ◽  
P. Muralidhar
Keyword(s):  
Motion Estimation ◽  
Video Coding ◽  
Video Compression ◽  
High Efficiency ◽  
Search Algorithm ◽  
Video Quality ◽  
Search Pattern ◽  
Absolute Difference ◽  
High Efficiency Video Coding ◽  
Search Patterns

High Efficiency Video Coding (HEVC) is a video compression standard that offers 50% more efficiency at the expense of high encoding time contrasted with the H.264 Advanced Video Coding (AVC) standard. The encoding time must be reduced to satisfy the needs of real-time applications. This paper has proposed the Multi- Level Resolution Vertical Subsampling (MLRVS) algorithm to reduce the encoding time. The vertical subsampling minimizes the number of Sum of Absolute Difference (SAD) computations during the motion estimation process. The complexity reduction algorithm is also used for fast coding the coefficients of the quantised block using a flag decision. Two distinct search patterns are suggested: New Cross Diamond Diamond (NCDD) and New Cross Diamond Hexagonal (NCDH) search patterns, which reduce the time needed to locate the motion vectors. In this paper, the MLRVS algorithm with NCDD and MLRVS algorithm with NCDH search patterns are simulated separately and analyzed. The results show that the encoding time of the encoder is decreased by 55% with MLRVS algorithm using NCDD search pattern and 56% with MLRVS using NCDH search pattern compared to HM16.5 with Test Zone (TZ) search algorithm. These results are achieved with a slight increase in bit rate and negligible deterioration in output video quality.

Parallel Full Search Algorithm for Motion Estimation on Graphic Processing Unit

2019 ◽  
Vol 12 (4) ◽  
pp. 317-323
Author(s):  
Fatma Ezzahra Sayadi ◽  
Marwa Chouchene ◽  
Haithem Bahri ◽  
Randa Khemiri ◽  
Mohamed Atri
Keyword(s):  
Motion Estimation ◽  
Video Compression ◽  
High Performance ◽  
High Efficiency ◽  
Search Algorithm ◽  
Low Cost ◽  
Video Quality ◽  
Processing Unit ◽  
High Efficiency Video Coding ◽  
Nvidia Gpu

Background: Advances in video compression technology have been driven by everincreasing processing power available in software and hardware. Methods: The emerging High-Efficiency Video Coding (HEVC) standard aims to provide a doubling in coding efficiency with respect to the H.264/AVC high profile, delivering the same video quality at half the bit rate. Results: Thus, the results show high computational complexity. In both standards, the motion estimation block presents a significant challenge in clock latency since it consumes more than 40% of the total encoding time. For these reasons, we proposed an optimized implementation of this algorithm on a low-cost NVIDIA GPU developed with CUDA language. Conclusion: This optimized implementation can provide high-performance video encoder where the speed reaches about 85.

FPGA-Based ROI Encoding for HEVC Video Bitrate Reduction

2020 ◽  
Vol 29 (11) ◽  
pp. 2050182
Author(s):  
Zhilei Chai ◽  
Shen Li ◽  
Qunfang He ◽  
Mingsong Chen ◽  
Wenjie Chen
Keyword(s):  
Data Storage ◽  
Video Compression ◽  
High Efficiency ◽  
Video Quality ◽  
Region Of Interest ◽  
Absolute Difference ◽  
High Efficiency Video Coding ◽  
High Definition ◽  
Mapping Algorithm ◽  
Block Based

The explosive growth of video applications has produced great challenges for data storage and transmission. In this paper, we propose a new ROI (region of interest) encoding solution to accelerate the processing and reduce the bitrate based on the latest video compression standard H.265/HEVC (High-Efficiency Video Coding). The traditional ROI extraction mapping algorithm uses pixel-based Gaussian background modeling (GBM), which requires a large number of complex floating-point calculations. Instead, we propose a block-based GBM to set up the background, which is in accord with the block division of HEVC. Then, we use the SAD (sum of absolute difference) rule to separate the foreground block from the background block, and these blocks are mapped into the coding tree unit (CTU) of HEVC. Moreover, the quantization parameter (QP) is adjusted according to the distortion rate automatically. The experimental results show that the processing speed on FPGA has reached a real-time level of 22 FPS (frames per second) for full high-definition videos ([Formula: see text]), and the bitrate is reduced by 10% on average with stable video quality.

scholarly journals Motion Estimation in HEVC/H.265: Metaheuristic Approach to Improve the Efficiency

2021 ◽  
Vol 12 (1) ◽  
pp. 59
Author(s):  
Khwaja Humble Hassan ◽  
Shahzad Ahmad Butt
Keyword(s):  
Motion Estimation ◽  
Video Coding ◽  
High Efficiency ◽  
Optimization Problems ◽  
Search Algorithm ◽  
High Efficiency Video Coding ◽  
High Definition ◽  
The Social ◽  
Test Zone ◽  
Encoding Efficiency

An ever increasing use of digital video applications such as video telephony, broadcast and the storage of high and ultra-high definition videos has steered the development of video coding standards. The state of the art video coding standard is High Efficiency Video Coding (HEVC) or otherwise known as H.265. It promises to be 50 percent more efficient than the previous video coding standard H.264. Ultimately, H.265 provides significant improvement in compression at the expense of computational complexity. HEVC encoder is very complex and 50 percent of the encoding consists of Motion Estimation (ME). It uses a Test Zone (TZ) fast search algorithm for its motion estimation, which compares a block of pixels with a few selected blocks in the search region of a referenced frame. However, the encoding time is not suitable to meet the needs of real time video applications. So, there is a requirement to improve the search algorithm and to provide comparable results to TZ search to save a substantial amount of time. In our paper, we aim to study the effects of a meta-heuristic algorithm on motion estimation. One such suitable algorithm for this task is the Firefly Algorithm (FA). FA is inspired by the social behavior of fireflies and is generally used to solve optimization problems. Our results show that implementing FA for ME saves a considerable amount of time with a comparable encoding efficiency.

scholarly journals Rate Distortion Performance of Motion Estimation for High Efficiency Video Coding

2019 ◽  
Vol 8 (2) ◽  
pp. 2855-2860
Keyword(s):  
Computational Complexity ◽  
Motion Estimation ◽  
Video Coding ◽  
High Efficiency ◽  
Search Algorithm ◽  
Rate Distortion ◽  
Objective Evaluation ◽  
Video Sequences ◽  
High Efficiency Video Coding ◽  
Different Types

The contemporary coding standard for video is High Efficiency Video Coding Standard (HEVC). It’s introduced by ITU-T (International Telegraph Union) and Joint Collaborative Team on Video Coding (JCT-VC). HEVC attains the requirement of video storage and transmission with high resolution. Although it requires the high amount of computational complexity. Motion Vectors are determined with motion estimation analysis; it is implemented with different types of algorithm. In this paper, Motion Estimation Process is implementing with the content split block search algorithm. It improves Peak Signal Noise Ratio (PSNR) than to the existing algorithms. The Objective evaluation has been performed with various video sequences such as BQ Terrace and also improved PSNR.

scholarly journals Low Power Oriented Full Search Block Based Motion Estimation (LP-FSBME) Architecture Using Power Efficient Adder Compressor For H.265 Coding Techniques.

2019 ◽  
Vol 9 (1S) ◽  
pp. 67-71
Keyword(s):  
Motion Estimation ◽  
Low Power ◽  
Video Coding ◽  
High Efficiency ◽  
Video Quality ◽  
Motion Vector ◽  
Absolute Difference ◽  
Power Efficient ◽  
Block Based ◽  
Full Search

H.265 coding is known as HIGH efficiency video coding (HEVC). This is most successful video compression standard and extended from H.264/MPEG-4 advanced video coding (AVC) for same level of video quality. However, H.265 improved better video quality for same bit rate. In video coding, motion estimation (ME) is determined the motion vector from adjacent frames. Various algorithms have been introduced by many researchers to accomplish low power oriented ME. However, low power oriented full search block based motion estimation (LP-FSBME) algorithm gives accurate results. Architecture of sum of absolute difference (SAD) is used an adder tree to accumulate the processing elements. Power efficient 16:2 adder compressors in SAD architecture reduce the power dissipation rather than convention adders in SAD architecture. The hardware implementation of proposed method is done in Xilinx Virtex 7 FPGA XC7VX1140T device with speed grade 1 in Xilinx software version 14.5 tool, developed in Verilog Hardware Description Language (Verilog-HDL), and simulated in ISE simulator for tennis, BQ terrace and Kimono videos with the resolution of 1080x720 pixels with 30fps.

Real-time motion estimation diamond search algorithm for the new high efficiency video coding on FPGA

2017 ◽  
Vol 94 (2) ◽  
pp. 259-276 ◽  
Author(s):  
Randa Khemiri ◽  
Hassan Kibeya ◽  
Hassen Loukil ◽  
Fatma Ezahra Sayadi ◽  
Mohamed Atri ◽  
...  
Keyword(s):  
Motion Estimation ◽  
Video Coding ◽  
Real Time ◽  
High Efficiency ◽  
Search Algorithm ◽  
High Efficiency Video Coding ◽  
Time Motion ◽  
Diamond Search ◽  
Diamond Search Algorithm
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