Self-reconfigurable control architecture for complex mobile robots

AbstractAdvanced mobile robot systems need to accomplish increasingly complex task sets. However, to solve demanding problems, they are typically optimized to a very restricted set of tasks and environments. This work will therefore propose a self-reconfigurable software and hardware architecture to allow the dynamic optimization of a robot system depending on the current situation, i. e. the current task, the robot inner state, and the environment. The proposed framework is based on organic computing principles and unsupervised machine learning techniques. It further uses dynamically reconfigurable Field Programmable Gate Arrays (FPGA) as hardware accelerators. Preliminary results will be presented, which demonstrate the feasibility of the self-reconfiguration approach.

Download Full-text

Dynamically Reconfigurable Embedded Architectures for Safe Transportation Systems

Advances in Systems Analysis, Software Engineering, and High Performance Computing - Handbook of Research on Embedded Systems Design ◽

10.4018/978-1-4666-6194-3.ch014 ◽

2014 ◽

pp. 347-371 ◽

Cited By ~ 2

Author(s):

Naim Harb ◽

Smail Niar ◽

Mazen A. R. Saghir

Keyword(s):

Integrated Circuits ◽

Embedded System ◽

Transportation Systems ◽

Base System ◽

Dynamic Partial Reconfiguration ◽

Dynamically Reconfigurable ◽

Gate Arrays ◽

Field Programmable ◽

Programmable Gate Arrays ◽

Mtt Algorithm

Embedded system designers are increasingly relying on Field Programmable Gate Arrays (FPGAs) as target design platforms. Today's FPGAs provide high levels of logic density and rich sets of embedded hardware components. They are also inherently flexible and can be easily and quickly modified to meet changing applications or system requirements. On the other hand, FPGAs are generally slower and consume more power than Application-Specific Integrated Circuits (ASICs). However, advances in FPGA architectures, such as Dynamic Partial Reconfiguration (DPR), are helping bridge this gap. DPR enables a portion of an FPGA device to be reconfigured while the device is still operating. This chapter explores the advantage of using the DPR feature in an automotive system. The authors implement a Driver Assistant System (DAS) based on a Multiple Target Tracking (MTT) algorithm as the automotive base system. They show how the DAS architecture can be adjusted dynamically to different scenario situations to provide interesting functionalities to the driver.

Download Full-text

EXTENDABLE AND DYNAMICALLY RECONFIGURABLE MULTI-PROTOCOL FIREWALL

International Journal of Software Engineering and Knowledge Engineering ◽

10.1142/s0218194005001926 ◽

2005 ◽

Vol 15 (02) ◽

pp. 363-371 ◽

Cited By ~ 2

Author(s):

SUNG LY ◽

ABBAS BIGDELI

Keyword(s):

Low Cost ◽

Local Network ◽

Gigabit Ethernet ◽

Dynamically Reconfigurable ◽

High Data ◽

Security Issues ◽

Field Programmable ◽

Programmable Gate Arrays ◽

And Performance ◽

Networking Technology

Security issues within a networking environment are critical, as attacks or intrusions can come from many different sources. Firewalls are an effective tool used for intrusion detection and provide protection against attacks on a system or network. In the past, protection barriers for a local network have been provided using software solutions. Emerging multi-gigabit networking technology and the high uptake of gigabit Ethernet has rendered these solutions inefficient as it cannot cope with the high data rate. In this paper, a new approach using reconfigurable hardware such as Field Programmable Gate Arrays is proposed to provide the flexibility and performance required for a gigabit firewall. The solution is extendable, has low cost and is capable of scanning multiple protocols. The design approach will allow it to be easily ported over to another family of chips with no or minor modification.

Download Full-text

Drone and sensor technology for sustainable weed management: a review

Chemical and Biological Technologies in Agriculture ◽

10.1186/s40538-021-00217-8 ◽

2021 ◽

Vol 8 (1) ◽

Author(s):

Marco Esposito ◽

Mariano Crimaldi ◽

Valerio Cirillo ◽

Fabrizio Sarghini ◽

Albino Maggio

Keyword(s):

Weed Management ◽

Yield Loss ◽

Abiotic Factors ◽

Machine Learning Techniques ◽

Sensor Technology ◽

Integrated Weed Management ◽

Weed Population Dynamics ◽

Learning Techniques ◽

Robot Systems ◽

Available Technology

AbstractWeeds are amongst the most impacting abiotic factors in agriculture, causing important yield loss worldwide. Integrated Weed Management coupled with the use of Unmanned Aerial Vehicles (drones), allows for Site-Specific Weed Management, which is a highly efficient methodology as well as beneficial to the environment. The identification of weed patches in a cultivated field can be achieved by combining image acquisition by drones and further processing by machine learning techniques. Specific algorithms can be trained to manage weeds removal by Autonomous Weeding Robot systems via herbicide spray or mechanical procedures. However, scientific and technical understanding of the specific goals and available technology is necessary to rapidly advance in this field. In this review, we provide an overview of precision weed control with a focus on the potential and practical use of the most advanced sensors available in the market. Much effort is needed to fully understand weed population dynamics and their competition with crops so as to implement this approach in real agricultural contexts.

Download Full-text

A simulation tool for dynamically reconfigurable field programmable gate arrays

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/92.532038 ◽

1996 ◽

Vol 4 (3) ◽

pp. 381-390 ◽

Cited By ~ 65

Author(s):

P. Lysaght ◽

J. Stockwood

Keyword(s):

Field Programmable Gate Arrays ◽

Simulation Tool ◽

Dynamically Reconfigurable ◽

Gate Arrays ◽

Field Programmable ◽

Programmable Gate Arrays

Download Full-text

Online scheduling and placement of hardware tasks with multiple variants on dynamically reconfigurable field-programmable gate arrays

Computers & Electrical Engineering ◽

10.1016/j.compeleceng.2013.07.004 ◽

2014 ◽

Vol 40 (4) ◽

pp. 1215-1237 ◽

Cited By ~ 9

Author(s):

Thomas Marconi

Keyword(s):

Field Programmable Gate Arrays ◽

Online Scheduling ◽

Dynamically Reconfigurable ◽

Gate Arrays ◽

Field Programmable ◽

Programmable Gate Arrays ◽

Multiple Variants

Download Full-text

An FPGA-Based Machine Learning Tool for In-Situ Food Quality Tracking Using Sensor Fusion

Biosensors ◽

10.3390/bios11100366 ◽

2021 ◽

Vol 11 (10) ◽

pp. 366

Author(s):

Daniel Enériz ◽

Nicolas Medrano ◽

Belen Calvo

Keyword(s):

Machine Learning ◽

Sensor Fusion ◽

Food Quality ◽

Low Cost ◽

Sensor Arrays ◽

Machine Learning Techniques ◽

Learning Techniques ◽

Field Programmable ◽

Single Field

The continuous development of more accurate and selective bio- and chemo-sensors has led to a growing use of sensor arrays in different fields, such as health monitoring, cell culture analysis, bio-signals processing, or food quality tracking. The analysis and information extraction from the amount of data provided by these sensor arrays is possible based on Machine Learning techniques applied to sensor fusion. However, most of these computing solutions are implemented on costly and bulky computers, limiting its use in in-situ scenarios outside complex laboratory facilities. This work presents the application of machine learning techniques in food quality assessment using a single Field Programmable Gate Array (FPGA) chip. The characteristics of low-cost, low power consumption as well as low-size allow the application of the proposed solution even in space constrained places, as in food manufacturing chains. As an example, the proposed system is tested on an e-nose developed for beef classification and microbial population prediction.

Download Full-text

Configurable Router Design for Dynamically Reconfigurable Systems based on the SoCWire NoC

International Journal of Reconfigurable and Embedded Systems (IJRES) ◽

10.11591/ijres.v2.i1.pp27-48 ◽

2013 ◽

Vol 2 (1) ◽

pp. 27 ◽

Cited By ~ 2

Author(s):

Arash Farhadi Beldachi ◽

Mohammad Hosseinabady ◽

Jose Luis Nunez-Yanez

Keyword(s):

Mesh Network ◽

Core System ◽

Dynamically Reconfigurable ◽

Gate Arrays ◽

Starting Point ◽

Field Programmable ◽

Programmable Gate Arrays ◽

Hardware Configuration ◽

Lower Complexity ◽

On Chip

New Field Programmable Gate Arrays (FPGAs) are capable of implementing complete multi-core System-on-Chip (SoC) with the possibility of modifying the hardware configuration at run-time with partial dynamic reconfiguration. The usage of a soft reconfigurable Network-on-Chip (NoC) to connect these cores is investigated in this paper. We have used a standard switch developed with the objective of supporting dynamically reconfigurable FPGAs as the starting point to create a novel configurable router. The configurable router uses distributed routing suitable for regular topologies and can vary the number of local ports and communication ports to build multi dimensional networks (i.e., 2D and 3D) with different topologies. The evaluation results show that the selection of the ideal router is different depending on traffic patterns and design objectives. Overall, the mesh network with a four local ports router offers a higher level of performance with lower complexity compared to the traditional mesh with one local port router.

Download Full-text

Functional Verification of Dynamic Partial Reconfiguration for Software-Defined Radio

Journal of Circuits System and Computers ◽

10.1142/s0218126621500420 ◽

2020 ◽

pp. 2150042

Author(s):

Islam Ahmed ◽

Ahmed Nader Mohieldin ◽

Hassan Mostafa

Keyword(s):

Software Defined Radio ◽

Computer Aided Design ◽

Functional Verification ◽

Partial Reconfiguration ◽

Dynamic Partial Reconfiguration ◽

Dynamically Reconfigurable ◽

Design Cycle ◽

Field Programmable ◽

Programmable Gate Arrays ◽

Aided Design

Dynamic Partial Reconfiguration (DPR) on Field Programmable Gate Arrays (FPGAs) allows reconfiguration of some of the logic at runtime while the rest of the logic keeps operating. This feature allows the designers to build complex systems such as Software-Defined Radio (SDR) in a reasonable area. New issues can arise due to usage of DPR technique such as guaranteeing proper connections for the ports of the Reconfigurable Modules (RMs) which share the same Reconfigurable Region (RR) on the FPGA, waiting for running computations on a module before reconfiguring it, isolation of the reconfigurable modules during the reconfiguration process, and initialization of the reconfigurable module after the reconfiguration process is done. Also, the Clock Domain Crossing (CDC) verification of the dynamically reconfigurable systems is a complicated task due to the need to verify all the modes of the designs, and the lack of Computer Aided Design (CAD) tools support for DRS designs. This paper summarizes our previous work to address these verification challenges for DPR. The approaches are demonstrated on a SDR system to show the effectiveness of applying these approaches in the design cycle.

Download Full-text