Third order intermodulation and third order intercept in a directly modulated Fabry–Perot laser diode

2020 ◽  
Vol 0 (0) ◽  
Author(s):  
Partha Pratim Pal ◽  
Meenakshi Chakraborty ◽  
Taraprasad Chattopadhyay

AbstractThis paper presents measurement of third order intermodulation distortion and third order intercept (TOI) in a Fabry–Perot semiconductor laser lasing at 1550.3 nm when the laser is biharmonically bias-current modulated. Keeping the modulation current of one signal fixed, the third order intermodulation power at two different frequencies has been found to increase with the increase in second signal modulation power. There is an eventual crossover or tendency to crossover in the intermodulation characteristics when the modulation current amplitudes of the channels assume the same value. The TOI has been experimentally measured. The intermodulation power appearing at two different frequencies along with their signal power dependence and measurement of TOI constitute the outcome of this paper. The typical value of spurious-free dynamic range of the modulation scheme is 70 dB.

2019 ◽  
Vol 0 (0) ◽  
Author(s):  
Sarika Singh ◽  
Sandeep K. Arya ◽  
Shelly Singla

AbstractA scheme to suppress nonlinear intermodulation distortion in microwave photonic (MWP) link is proposed by using polarizers to compensate inherent non-linear behavior of dual-electrode Mach-Zehnder modulator (DE-MZM). Insertion losses and extinction ratio have also been considered. Simulation results depict that spurious free dynamic range (SFDR) of proposed link reaches to 130.743 dB.Hz2/3. A suppression of 41 dB in third order intermodulation distortions and an improvement of 15.3 dB is reported when compared with the conventional link. In addition, an electrical spectrum at different polarization angles is extracted and 79^\circ is found to be optimum value of polarization angle.


Author(s):  
Ruiqiong Wang ◽  
Yangyu Fan ◽  
Jiajun Tan ◽  
Yongsheng Gao

2013 ◽  
Vol 473 ◽  
pp. 50-53
Author(s):  
Jie Lin ◽  
Fei Yan Mu

A high accuracy BiCMOS sample and hold (S/H) circuit employed in the front end of a12bit 10 MS/s Pipeline ADC is presented. To reduce the nonlinearity error cause by the sampling switch, a signal dependent clock bootstrapping system is introduced. It is implemented using 0.6 um BiCMOS process. An 88.77 dB spurious-free dynamic range (SFDR), and a -105.20 dB total harmonic distortion (THD) are obtained.


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