Spurious-free dynamic range improvement in a photonic time-stretched analog-to-digital converter based on third-order predistortion

2014 ◽  
Vol 2 (5) ◽  
pp. 97 ◽  
Author(s):  
Boyu Xu ◽  
Wulue Lv ◽  
Jiamu Ye ◽  
Jinhai Zhou ◽  
Xiaofeng Jin ◽  
...  
Keyword(s):  
Dynamic Range ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Third Order ◽  
Analog To Digital ◽  
Spurious Free Dynamic Range ◽  
Free Dynamic

A LOW POWER 13-BIT 50MS/s RECIRCULATING PIPELINE ANALOG TO DIGITAL CONVERTER

2014 ◽  
Vol 23 (06) ◽  
pp. 1450090 ◽  
Author(s):  
ARASH ESMAILI ◽  
HADISEH BABAZADEH ◽  
KHAYROLLAH HADIDI ◽  
ABDOLLAH KHOEI
Keyword(s):  
Power Consumption ◽  
Dynamic Range ◽  
Cmos Technology ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Nyquist Frequency ◽  
Signal To Noise ◽  
Analog To Digital ◽  
Spurious Free Dynamic Range ◽  
Free Dynamic

A 13-bit analog-to-digital converter (ADC) is designed in 0.35 μm CMOS technology that reduces the power consumption through sharing the resources between pipeline stages. Using a dummy sample-and-hold (S/H) and recirculating concept the requirements for the first stage are relaxed and the design restrictions are resolved. This ADC does not use a dedicated S/H and reaches a speed of 50 MS/s. The design is tested with TSMC mixed-signal 0.35 μm technology and post layout simulations shows over 75 dB Signal-to-Noise and Distortion-Ratio (SNDR) and over 85 dB Spurious Free Dynamic Range (SFDR) at the Nyquist frequency. The designed chip occupies an area of 1.3 mm–0.7 mm and consumes 164 mW power at Nyquist from a 3.3 V supply.

scholarly journals Effects of ADC Nonlinearity on the Spurious Dynamic Range Performance of Compressed Sensing

2014 ◽  
Vol 2014 ◽  
pp. 1-6 ◽  
Author(s):  
Rongzong Kang ◽  
Pengwu Tian ◽  
Hongyi Yu
Keyword(s):  
Compressed Sensing ◽  
Dynamic Range ◽  
Dynamic Performance ◽  
Digital Converter ◽  
Analog To Digital ◽  
Sensing System ◽  
Spurious Free Dynamic Range ◽  
Simulation Results ◽  
The Impact ◽  
Free Dynamic

Analog-to-information converter (AIC) plays an important role in the compressed sensing system; it has the potential to significantly extend the capabilities of conventional analog-to-digital converter. This paper evaluates the impact of AIC nonlinearity on the dynamic performance in practical compressed sensing system, which included the nonlinearity introduced by quantization as well as the circuit non-ideality. It presents intuitive yet quantitative insights into the harmonics of quantization output of AIC, and the effect of other AIC nonlinearity on the spurious dynamic range (SFDR) performance is also analyzed. The analysis and simulation results demonstrated that, compared with conventional ADC-based system, the measurement process decorrelates the input signal and the quantization error and alleviate the effect of other decorrelates of AIC, which results in a dramatic increase in spurious free dynamic range (SFDR).

scholarly journals A 3GSps 12-bit Four-Channel Time-Interleaved Pipelined ADC in 40 nm CMOS Process

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1551 ◽  
Author(s):  
Jianwen Li ◽  
Xuan Guo ◽  
Jian Luan ◽  
Danyu Wu ◽  
Lei Zhou ◽  
...  
Keyword(s):  
Dynamic Range ◽  
Cmos Process ◽  
Pipelined Adc ◽  
Least Significant Bit ◽  
Analog To Digital ◽  
Capacitor Mismatch ◽  
Gain Error ◽  
Spurious Free Dynamic Range ◽  
Time Interleaved ◽  
Free Dynamic

This paper presents a four-channel time-interleaved 3GSps 12-bit pipelined analog-to-digital converter (ADC). The combination of master clock sampling and delay-adjusting is adopted to remove the time skew due to channel mismatches. An early comparison scheme is used to minimize the non-overlapping time, where a custom-designed latch is developed to replace the typical non-overlapping clock generator. By using the dither capacitor to generate an equivalent direct current input, a zero-input-based calibration is developed to correct the capacitor mismatch and inter-stage gain error. Fabricated in a 40 nm CMOS process, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 57.8 dB and a spurious free dynamic range (SFDR) of 72 dB with a 23 MHz input tone. It can achieve an SNDR above 52.3 dB and an SFDR above 61.5 dB across the entire first Nyquist zone. The differential and integral nonlinearities are −0.93/+0.73 least significant bit (LSB) and −2.8/+4.3 LSB, respectively. The ADC consumes 450 mW powered at 1.8V, occupies an active area of 3 mm × 1.3 mm. The calculated Walden figure of merit reaches 0.44 pJ/step.

scholarly journals Odd/Even Order Sampling Soft-Core Architecture towards Mixed Signals Fourth Industrial Revolution (4IR) Applications

Energies ◽  
2019 ◽  
Vol 12 (23) ◽  
pp. 4567
Author(s):  
Mfana ◽  
Hasan ◽  
Ali
Keyword(s):  
Industrial Revolution ◽  
Dynamic Range ◽  
Sampling Frequency ◽  
Sampling Techniques ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Sigma Delta ◽  
Analog To Digital ◽  
Fourth Industrial Revolution ◽  
Even Order

Digitization is at the center of fourth industrial revolution (4IR) with previously analog systems being digitized through an analog-to-digital converter. In addition, 4IR applications such as fifth generation (5G) Cellular Networks Technology and Cognitive Electronic Warfare (EW) at some point interface digitally through an analog-to-digital converter. Efficient use of digital resources such as memory, largely depends on the signal sampling design of analog-to-digital converters. Existing even order sampling has been found to perform better than traditional sampling techniques. Research on the efficiency of a digital interface with a 4IR platform is still in its infancy. This paper presents a performance study of three sampling techniques: the proposed new and novel odd/even order sampling architecture, existing Mod-∆, and traditional 1st order delta-sigma, to address this. Step-size signal-to-noise (SNR), dynamic range, and sampling frequency are also studied. It was found that the proposed new and novel odd/even order sampling achieved an SNR performance of 6 dB in comparison to 18 dB for Mod-∆. Sampling frequency findings indicated that the proposed new and novel odd/even order sampling achieved a sampling frequency of 2 kHz in comparison to 8 kHz from a traditional 1st order sigma-delta. Dynamic range findings indicated that the proposed odd/even order sampling has achieved a dynamic range of 1.088 volts/ms in comparison to 1.185 volts/ms from a traditional 1st order sigma-delta. Findings have indicated that the proposed odd/even order sampling has superior SNR and sampling frequency performances, while the dynamic range is reduced by 8%.

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