A Proposal of a New Gradient Driver with a Gradational Voltage Inverter for Low Power Loss

2021 ◽  
Vol 141 (12) ◽  
pp. 942-951
Author(s):  
Masayuki Oishi ◽  
Ryosuke Kobayashi ◽  
Tomokazu Sakashita
2010 ◽  
Vol 130 (9) ◽  
pp. 1630-1635
Author(s):  
Takayuki Hashimoto ◽  
Tetsuya Kawashima ◽  
Masaki Shiraishi ◽  
Noboru Akiyama ◽  
Tomoaki Uno ◽  
...  

Author(s):  
Yudai Abe ◽  
Akio Iwabuchi ◽  
Jun-Ichi Matsuda ◽  
Anna Kuwana ◽  
Takashi Ida ◽  
...  

2020 ◽  
Vol 475 ◽  
pp. 126282 ◽  
Author(s):  
Qinfeng Zhao ◽  
Wenqi Yu ◽  
Yiru Zhao ◽  
Shuangxing Dai ◽  
Jianguo Liu

2020 ◽  
Vol 1004 ◽  
pp. 776-782
Author(s):  
Kosuke Uchida ◽  
Toru Hiyoshi ◽  
Yu Saito ◽  
Hiroshi Egusa ◽  
Tatsushi Kaneda ◽  
...  

1200 V / 200 A V-groove trench MOSFET optimized to achieve low power loss, high oxide reliability under a drain bias condition and high avalanche ruggedness is shown in this paper. We revealed a relationship between the lifetime under a high temperature reverse bias condition and the oxide electric field. In accordance with the results of the test, the 1200 V / 200 A trench MOSFET showed an improvement in the tradeoff between the on-resistance and oxide electric field with the presence of current spreading layers. In order to obtain low on-resistance and high avalanche ruggedness at the same time, buried guard ring structures, which made the blocking voltage of the edge termination area higher than that of the active area, was developed. The fabricated MOSFETs demonstrated a low specific on-resistance of 3.1 mΩ cm2. A predicted lifetime of 200 years under a high temperature drain bias condition of 1200 V was achieved by the optimized design. A short circuit withstand time of 6 μs and a high avalanche energy of 7.8 J/cm2 were shown.


2012 ◽  
Vol 468-471 ◽  
pp. 891-894
Author(s):  
Lin He ◽  
Kun Ning Jia ◽  
Zun Qiang Fan

Low power loss is the key of loop powered transducer design. The methods for reducing power loss are discussed in this paper. By selecting the appropriate device, and ultimately achieve the purpose of reducing energy loss. By the measured, the design fully meets the system requirements.


Author(s):  
C.A. Pirrie ◽  
P.D. Culling ◽  
H. Menown ◽  
R. Sheldrake

2008 ◽  
Vol 67 (1) ◽  
pp. 17-20
Author(s):  
Sameer Yadav ◽  
Ishwinder Pal Singh ◽  
O. P. Pandey

2019 ◽  
Vol 17 (10) ◽  
pp. 826-831
Author(s):  
Vandana Shukla ◽  
O. P. Singh ◽  
G. R. Mishra ◽  
R. K. Tiwari

Low power high speed calculating devices are foremost requirement of this era. Moreover, multiplication is considered as the most vital part of any calculating system. Multiplication process is generally considered as the speed limiting process as it requires more time as compared to other basic arithmetic calculations. So, here we focus on multiplication calculation using vedic method. Moreover, Reversible realization of any digital circuit improves the performance of the system by reducing the power loss from it. Here, the concept of vedic multiplication and Reversible approach are combined to propose a 4-bit multiplier circuit with optimized performance parameters. Proposed design is also analyzed and compared with existing designs. This approach may be employed to propose other low loss devices.


2013 ◽  
Vol 84 (8) ◽  
pp. 413-417
Author(s):  
Yu. Yu. Tsykunov
Keyword(s):  

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