Deep Level Characterization and Passivation in Heteroepitaxial Inp

1993 ◽  
Vol 325 ◽  
Author(s):  
B. Chatterjee ◽  
S. A. Ringel ◽  
R. Sieg ◽  
I. Weinberg ◽  
R. Hoffman

AbstractDeep levels in MOCVD grown p-InP on GaAs substrates have been investigated by Deep Level Transient Spectroscopy (DLTS). The effect of hydrogenation on the electrical activity of these levels has been studied through a combination of DLTS and Photoluminescence (PL) measurements. DLTS measurements indicate a drop of trap density from σ 5 × 1014 cm−3 to σ 1 × 1012 cm−3 after hydrogenation. Annealing at 400°C reactivated only the dopants, while temperatures above 600°C were necessary for deep-level reactivation. This combined with a logarithmic dependence on fill pulse time, indicate that at least one broad DLTS peak is associated with dislocations. The PL the DLTS results show that the dislocation related traps are passivated by hydrogen, preferentially over the dopants and that a wide annealing window exists for dopant reactivation.

Author(s):  
N. Chinone ◽  
Y. Cho ◽  
R. Kosugi ◽  
Y. Tanaka ◽  
S. Harada ◽  
...  

Abstract A new technique for local deep level transient spectroscopy (DLTS) imaging using super-higher-order scanning nonlinear dielectric microscopy is proposed. Using this technique. SiCVSiC structure samples with different post oxidation annealing conditions were measured. We observed that the local DLTS signal decreases with post oxidation annealing (POA), which agrees with the well-known phenomena that POA reduces trap density. Furthermore, obtained local DLTS images had dark and bright areas, which is considered to show the trap distribution at/near SiCVSiC interface.


2010 ◽  
Vol 645-648 ◽  
pp. 759-762
Author(s):  
Koutarou Kawahara ◽  
Giovanni Alfieri ◽  
Michael Krieger ◽  
Tsunenobu Kimoto

In this study, deep levels are investigated, which are introduced by reactive ion etching (RIE) of n-type/p-type 4H-SiC. The capacitance of as-etched p-type SiC is remarkably small due to compensation or deactivation of acceptors. These acceptors can be recovered to the initial concentration of the as-grown sample after annealing at 1000oC. However, various kinds of defects remain at a total density of ~5× 1014 cm-3 in a surface-near region from 0.3 μm to 1.0 μm even after annealing at 1000oC. The following defects are detected by Deep Level Transient Spectroscopy (DLTS): IN2 (EC – 0.35 eV), EN (EC – 1.6 eV), IP1 (EV + 0.35 eV), IP2 (HS1: EV + 0.39 eV), IP4 (HK0: EV + 0.72 eV), IP5 (EV + 0.75 eV), IP7 (EV + 1.3 eV), and EP (EV + 1.4 eV). These defects generated by RIE can be significantly reduced by thermal oxidation and subsequent annealing at 1400oC.


2001 ◽  
Vol 90 (7) ◽  
pp. 3377-3382 ◽  
Author(s):  
A. Kawasuso ◽  
F. Redmann ◽  
R. Krause-Rehberg ◽  
T. Frank ◽  
M. Weidner ◽  
...  

1982 ◽  
Vol 14 ◽  
Author(s):  
P. H. Campbell ◽  
O. Aina ◽  
B. J. Baliga ◽  
R. Ehle

ABSTRACTHigh temperature annealing of Si 3 N4 and SiO2 capped high purity LPE GaAs is shown to result in a reduction in the surface carrier concentration by about an order of magnitude. Au Schottky contacts made on the annealed samples were found to have severely degraded breakdown characteristics. Using deep level transient spectroscopy, deep levels at EC–.58eV, EC–.785eV were detected in the SiO2, capped samples and EC–.62eV, EC–.728eV in the Si3N4 capped Samples while none was detected in the unannealed samples.The electrical degradations are explained in terms of compensation mechanisns and depletion layer recombination-generation currents due to the deep levels.


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