High Voltage Effects in Top Gate Amorphous Silicon Thin Film Transistors

2000 ◽  
Vol 621 ◽  
Author(s):  
N. Tosic ◽  
F. G. Kuper ◽  
T. Mouthaan

ABSTRACTIn this paper, an analysis of the high voltage induced degradation in top gate amorphous silicon Thin Film Transistors (TFT) will be shown, including the aspect of self-heating. It will be shown through experimental results that the degradation level under high voltages on drain and gate is different for TFT's with different channel lengths. In addition, the temperature distribution over the TFT area for devices with different channel length is simulated. Simulation shows that the peak of temperature distribution is located at the drain/channel edge and that level of thermal heating depends on the channel length.

1991 ◽  
Vol 69 (4) ◽  
pp. 2667-2672 ◽  
Author(s):  
John G. Shaw ◽  
Michael G. Hack ◽  
Russel A. Martin

1993 ◽  
Vol 40 (3) ◽  
pp. 634-644 ◽  
Author(s):  
R.A. Martin ◽  
V.M. Da Costa ◽  
M. Hack ◽  
J.G. Shaw

1992 ◽  
Vol 31 (Part 1, No. 11) ◽  
pp. 3506-3510 ◽  
Author(s):  
Yoshiyuki Kaneko ◽  
Tooru Toyabe ◽  
Toshihisa Tsukada

1990 ◽  
Vol 192 ◽  
Author(s):  
M. Hack ◽  
W. B. Jackson ◽  
R. Lujan

ABSTRACTWe have developed a means to speed up the recovery of both the threshold voltage shift of hydrogenated amorphous silicon (a-Si:H) transistors and the Vx shift of high voltage a-Si devices. This is accomplished by placing a lightly doped compensated layer adjacent to the active layer in these transistors. This proximity recovery layer does not alter the initial characteristics of a-Si:H transistors and is completely process compatible with standard fabrication procedures.


2007 ◽  
Vol 989 ◽  
Author(s):  
Jian-Zhang Chen ◽  
I-Chun Cheng ◽  
Sigurd Wagner ◽  
Warren Jackson ◽  
Craig Perlov ◽  
...  

AbstractWe studied the effect of prolonged mechanical strain on the electrical characteristics of thin-film transistors of hydrogenated amorphous silicon made at a process temperature of 150°C on 51-μm thick Kapton polyimide foil substrates. Effects are observed only at very high compressive strain of 1.8%. Tensile strain up to fracture at 0.3% to 0.5% does not show any effect, nor does compressive strain substantially less than 1.8%. The TFTs were stressed for times up to 23 days by bending around a tube with axis perpendicular to the channel length, and were evaluated in the flattened state. The changes observed are small. The threshold voltage is increased, the “on” current and the field effect mobility remain essentially constant, and the subthreshold slope, “off” current and gate leakage current drop somewhat. Overall, the observed changes are small. We conclude that mechanical strain caused by roll-to-roll processing and permanent shaping will have negligible effects on TFT performance.


1998 ◽  
Vol 83 (7) ◽  
pp. 3660-3667 ◽  
Author(s):  
J. Rhayem ◽  
M. Valenza ◽  
D. Rigaud ◽  
N. Szydlo ◽  
H. Lebrun

1994 ◽  
Vol 336 ◽  
Author(s):  
H.S. Choi ◽  
Y.S. Kim ◽  
S.K. Lee ◽  
J.K. Yoon ◽  
W.S. Park ◽  
...  

ABSTRACTThe effects of top-insulator on the instability problems of hydrogenated amorphous silicon (a-Si:H) thin film transistors (TFTs) have been studied. In a-Si:H TFT with top-insulator (E/S type), charge trapping into the both of top-insulator and gate insulator has been shown under the bias stress.In order to investigate the charge trapping effects of top-insulator, we proposed a new method of Measurement. By this Method, we observed that trapped charges in top-insulator increased drain currents for positive gate bias stress, and this increment of drain currents was more serious with increasing the ratio of source/drain overlap length to channel length. It has founded that the instability problems of a-Si:H TFTs was attributed to the effects of top-insulator as well as that of gate insulator.


1998 ◽  
Vol 507 ◽  
Author(s):  
Hyuk-Ryeol Park ◽  
J. David Cohen

ABSTRACTThe inter-electrode capacitance - voltage (C-V) characteristics of back-channel etched inverted-staggered hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) were investigated. It is demonstrated that this simple measurement can be used to diagnose TFT parameters such as the fabricated channel length, the channel resistance, and the error in the mask alignment of the source and drain overlap lengths. The C-V characteristics associated with the hole accumulation in a-Si:H TFTs with n+-type source/drain contacts were also examined. We observed that the a.c. capacitance increases for low frequencies and/or moderately high measurement temperatures provided the gate voltage is sufficiently negative.


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