High Voltage Effects in Top Gate Amorphous Silicon Thin Film Transistors
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ABSTRACTIn this paper, an analysis of the high voltage induced degradation in top gate amorphous silicon Thin Film Transistors (TFT) will be shown, including the aspect of self-heating. It will be shown through experimental results that the degradation level under high voltages on drain and gate is different for TFT's with different channel lengths. In addition, the temperature distribution over the TFT area for devices with different channel length is simulated. Simulation shows that the peak of temperature distribution is located at the drain/channel edge and that level of thermal heating depends on the channel length.
1989 ◽
Vol 115
(1-3)
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pp. 141-143
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1993 ◽
Vol 40
(3)
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pp. 634-644
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1992 ◽
Vol 31
(Part 1, No. 11)
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pp. 3506-3510
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2009 ◽
Vol 4
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pp. 227-233
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