scholarly journals A 14bit 500MS/s 85.62dBc SFDR 66.29dB SNDR SHA-less pipelined ADC with a stable and high-linearity input buffer and aperture-error calibration in 40nm CMOS

2021 ◽  
Author(s):  
Mingliang Chen ◽  
Keke Wu ◽  
Yupeng Shen ◽  
Zhiyu Wang ◽  
Hua Chen ◽  
...  
Keyword(s):  
Pipelined Adc ◽  
Input Buffer ◽  
High Linearity ◽  
Error Calibration

Fast digital foreground gain error calibration for pipelined ADC

2019 ◽  
Vol 13 (2) ◽  
pp. 219-225
Author(s):  
Jupinder Kaur ◽  
Prince Prabhakar ◽  
Anil Singh ◽  
Alpana Agarwal
Keyword(s):  
Pipelined Adc ◽  
Gain Error ◽  
Error Calibration

An 11-b 100-MS/s Fully Dynamic Pipelined ADC Using a High-Linearity Dynamic Amplifier

2020 ◽  
Vol 55 (9) ◽  
pp. 2468-2477
Author(s):  
Yunsoo Park ◽  
Jaegeun Song ◽  
Yohan Choi ◽  
Chaegang Lim ◽  
Soonsung Ahn ◽  
...  
Keyword(s):  
Pipelined Adc ◽  
High Linearity

A High-Linearity Pipelined ADC With Opamp Split-Sharing in a Combined Front-End of S/H and MDAC1

2013 ◽  
Vol 60 (11) ◽  
pp. 2834-2844 ◽  
Author(s):  
Zhenyu Wang ◽  
Mingshuo Wang ◽  
Weiru Gu ◽  
Chixiao Chen ◽  
Fan Ye ◽  
...  
Keyword(s):  
Pipelined Adc ◽  
High Linearity ◽  
Front End

A CMOS Input Buffer for High-Resolution A/D Converters with High Sampling Rates

2014 ◽  
Vol 678 ◽  
pp. 497-500
Author(s):  
Xing Fa Huang ◽  
Rong Bin Hu ◽  
Liang Li
Keyword(s):  
High Resolution ◽  
Input Signal ◽  
High Speed ◽  
Process Technology ◽  
Input Buffer ◽  
Design And Implementation ◽  
High Linearity ◽  
High Sampling

With respect to the application of high-speed, high-resolution A/D converter, the design and implementation of a CMOS input buffer is introduced. The buffer features high-speed and high-linearity. Its performances have been verified in a 14-bit 250MSPS pipelined A/D converter which is developed in 0.18um CMOS-based process technology. The simulation shows that the SFDR of the buffer is up to 104dB at an input clock of 250MHz with an input signal of 25MHz.

scholarly journals A High‐linearity Input‐Buffer with high output common‐mode stability for 10bit 3.2GSs ADC

2020 ◽  
Vol 56 (13) ◽  
pp. 653-655 ◽  
Author(s):  
Ting Sun ◽  
Jing Li ◽  
Ning Ning ◽  
Kejun Wu ◽  
Qi Yu
Keyword(s):  
Input Buffer ◽  
Common Mode ◽  
High Linearity ◽  
Mode Stability ◽  
High Output
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